SWCU193 April 2023 CC2340R2 , CC2340R5 , CC2340R5-Q1
Table 2-40 lists the memory-mapped registers for the DCB registers. All register offset addresses not listed in Table 2-40 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | DFSR | Debug Fault Status Register | Go |
C0h | DHCSR | Debug Halting Control and Status Register | Go |
C4h | DCRSR | Debug Core Register Selector Register | Go |
C8h | DCRDR | Debug Core Register Data Register | Go |
CCh | DEMCR | Debug Exception and Monitor Control Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 2-41 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
DFSR is shown in Table 2-42.
Return to the Summary Table.
Debug Fault Status Register
Use the Debug Fault Status Register to monitor external debug requests, vector catches, data watchpoint match, BKPT instruction execution and BPU comparator matches, halt requests. Write one to clear. C_DEBUGEN must be set before any bits in DFSR are updated.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | EXTERNAL | R/W | 0h | External debug request flag 0x0:No edbgrq external debug request occurred 0x1:Edbgrq has halted the core |
3 | VCATCH | R/W | 0h | Vector catch flag. When the VCATCH flag is set, a flag in the Debug Exception and Monitor Control Register is also set to indicate the type of vector catch. 0x0:No vector catch occurred 0x1:Vector catch occurred |
2 | DWTRAP | R/W | 0h | Data Watchpoint (DW) flag. 0x0:No dw match 0x1:Dw match |
1 | BKPT | R/W | 0h | The BKPT flag is set by the execution of the BKPT instruction or on an instruction whose address triggered the breakpoint comparator match. When the processor has halted, the return PC points to the address of the breakpointed instruction. 0x0:No bkpt instruction or hardware breakpoint match 0x1:Bkpt instruction or hardware breakpoint match |
0 | HALTED | R/W | 0h | Halt request flag 0x0:No halt request 0x1:Halt requested by dap access to c_halt or halted with c_step asserted |
DHCSR is shown in Table 2-43.
Return to the Summary Table.
Debug Halting Control and Status Register
The purpose of the Debug Halting Control and Status Register (DHCSR) is to provide status information about the state of the processor, enable core debug, halt and step the processor. For writes, 0xA05F must be written to bits [31:16], otherwise the write operation is ignored and no bits are written into the register.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | Reserved |
25 | S_RESET_ST | R | 0h | Indicates that the core has been reset, or is now being reset, since the last time this bit was read. This a sticky bit that clears on read. So, reading twice and getting 1 then 0 means it was reset in the past. Reading twice and getting 1 both times means that it is currently reset and held in reset. |
24 | S_RETIRE_ST | R | 0h | Core has retired at least part of an instruction since last read. This is a sticky bit that clears on read. |
23-18 | RESERVED | R | 0h | Reserved |
17 | S_HALT | R | 0h | The core is halted in debug state only if S_HALT is set. |
16 | S_REGRDY | R | 0h | Register Read/Write to the Debug Core Register Selector Register is available. Set in response to a successful register access. |
15-4 | RESERVED | R | 0h | Reserved |
3 | C_MASKINTS | R/W | 0h | When this bit is set and debug is enabled, external interrupts, SysTick, and PendSV are masked. Does not affect NMI, Hard Fault or SVCall. When C_DEBUGEN = 0, this bit has no effect. |
2 | C_STEP | R/W | 0h | Causes a debug event on any instruction or exception being executed, resulting in the core single stepping. |
1 | C_HALT | R/W | 0h | Halts the core. This bit is set automatically when the core triggers a debug event, for example, on a breakpoint. This bit clears on core reset. When C_DEBUGEN = 0, this bit has no effect. |
0 | C_DEBUGEN | R/W | 0h | Enables or disable debug
0h = Debug disabled 1h = Debug enabled |
DCRSR is shown in Table 2-44.
Return to the Summary Table.
Debug Core Register Selector Register
The purpose of the Debug Core Register Selector Register (DCRSR) is to select the processor register to transfer data to or from.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | Reserved |
16 | REGWnR | W | 0h | Register Write-not-Read 0x0:Read 0x1:Write |
15-5 | RESERVED | R | 0h | Reserved |
4-0 | REGSEL | W | 0h | Select processor register 0x00:R0 0x01:R1 0x02:R2 0x03:R3 0x04:R4 0x05:R5 0x06:R6 0x07:R7 0x08:R8 0x09:R9 0x0a:R10 0x0b:R11 0x0c:R12 0x0d:Current sp 0x0e:Lr 0x0f:Debug Return Address 0x10:Xpsr flags, execution number, and state information 0x11:Msp (main sp) 0x12:Psp (process sp) 0x14:Control (dcrdr[25:24]), primask (dcrdr[0]) |
DCRDR is shown in Table 2-45.
Return to the Summary Table.
Debug Core Register Data Register
The purpose of the Debug Core Register Data Register (DCRDR) is to hold data read from or written to core registers.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DBGTMP | R/W | 0h | Data temporary cache, for reading and writing registers. |
DEMCR is shown in Table 2-46.
Return to the Summary Table.
Debug Exception and Monitor Control Register
The purpose of the Debug Exception and Monitor Control Register (DEMCR) is: Global enable for the DW unit, Vector catching (that is, causes debug entry on execution of a specified vector.)
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | DWTENA | R/W | 0h | Global enable or disable for the DW unit 0x0:Dw unit disabled. watchpoint cannot halt the core. the dw pcsr reads as oxffffffff. 0x1:Dw unit enabled |
23-11 | RESERVED | R | 0h | Reserved |
10 | VC_HARDERR | R/W | 0h | Debug trap on a Hard Fault |
9-1 | RESERVED | R | 0h | Reserved |
0 | VC_CORERESET | R/W | 0h | Reset Vector Catch. Halt running system if HRESETn is asserted |