SWCU193 April 2023 CC2340R2 , CC2340R5 , CC2340R5-Q1
When the UART.CTL[1] SIREN bit is set, the IrDA (SIR) encoder and decoder are enabled and provide hardware bit shaping for IrDA communication. In this protocol, from the transmitter perspective, a zero is transmitted as a high pulse and a one is transmitted as a zero.
The width of the pulse is specified as 3/16th of the selected bit period. The SIR decoder converts the IrDA compliant receive signal into a bit stream for the UART core. The SIR receive logic interprets a high state as a logic one and low pulses as logic zeros. For more details please refer to the SIR Physical Layer Link Specification Version 1.1
Setting the UART.CTL SIRLP[2] bit enables low power mode. In the low power mode, the width of the pulse is set to 3 times the time period of the IrLPBaud16 signal. The IrLPBaud16 signal is generated by dividing down the CLKSVT (48MHz) according to the low-power divisor value written to the UARTILPR register. The low-power divisor value is calculated as follows:
where FIrLPBaud16 is nominally 1.8432 MHz.
The divisor must be selected such that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, results in a low-power pulse duration of 1.41-2.11μs (three times the period of IrLPBaud16).
The time period of the nSIROUT bit stream is still equal to the programmed bit period and is governed by the period of the Baud16 signal.
In the low power mode, there is an upper limit on the allowable bit rate if the integrity of the IrDA pulse stream is to be maintained. The upper limit is determined by the requirement that the width of 3 times the period of the IrLPBaud16 signal is less than one bit period. With a nominal IrLPBaud16 frequency of 2 MHz, this translates to a maximum allowable baud rate of 666.6 Kbps. This is not a problem since the specification states that the UART is to support bit rates of only up to 115.2 Kbps for the SIR endec.
If the low power mode of the IrDA is used, there is also a lower limit on the frequency of CLKSVT. The reload value for the IrLPBaud16 counter can be a minimum of 1. Given that IrLPBaud16 needs to have a minimum frequency of 1.42 MHz to satisfy IrDA requirements, CLKSVT needs to be at least 1.42 MHz to meet the minimum pulse width requirement. In the case of transmission, the IrLPBaud16 signal is used to control the width of the transmit pulse stream only in the low power mode. On the other hand, in the case of reception, the IrLPBaud16 signal is used to sample the pulses in the input SIRIN stream both in the normal mode and in the low power mode. Thus, the IrLPBaud16 signal is generated irrespective of whether the IrDA section is programmed to operate in the normal mode or in the low power mode but the signal is not generated when both IrDA modes are disabled.
The SIR receiver section contains a 4-bit binary counter, which operates on CLKSVT in the normal mode with the Baud16 signal as an enable signal. When the input SIRIN signal is high, the decoded output signal, RXD, is driven high to indicate a 1. A low on the SIRIN line is sampled multiple times on IrLPBaud16 for glitch rejection and converted into a low on the RXD line. The time period for which the RXD line is pulled low corresponds to approximately one bit period at the programmed bit rate. After the counter rolls over, input sampling restarts. The SIRLPSync signal is the CLKSVT-synchronised version of the SIRLP mode selection bit in the UART.CTL register. This signal determines the IrDA encoding strategy i.e. whether the IrDA transmitter block is to operate in the normal mode or in the low power mode. The SIRENSync signal is the SIREN bit in the UART.CTL register, which has been synchronised to CLKSVT. This signal enables / disables the SIR section.