TIDUF59 March   2024

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 PFC Inductance Design
      2. 2.2.2 Configuration of CS pin in LMG3622
      3. 2.2.3 AHB Topology and the VCC Design
      4. 2.2.4 LMG2610 for AHB Topology
    3. 2.3 Highlighted Products
      1. 2.3.1 UCC28056
      2. 2.3.2 LMG3622
      3. 2.3.3 LMG2610
  9. 3Hardware, Test Requirements, and Test Results
    1. 3.1 Hardware
    2. 3.2 Test Setup
    3. 3.3 Test Results
      1. 3.3.1 Switching Waveform
        1. 3.3.1.1 Switching Waveform on the PFC Stage
        2. 3.3.1.2 Switching Waveform on the AHB Stage
      2. 3.3.2 Efficiency Test Result
      3. 3.3.3 Thermal Test Result
  10. 4Design and Documentation Support
    1. 4.1 Design Files
      1. 4.1.1 Schematics
      2. 4.1.2 BOM
      3. 4.1.3 Layout Prints {Optional Section}
    2. 4.2 Tools
    3. 4.3 Documentation Support
    4. 4.4 Support Resources
    5. 4.5 Trademarks
  11. 5About the Author

UCC28056

GUID-20211202-SS0I-QNTX-HVC3-VVG2GCNJ1HMK-low.gif Figure 2-9 Simplified Application Circuit Diagram

The UCC28056 device drives PFC boost stages based on a mixed mode method that operates in TM and discontinuous conduction mode (DCM) at reduced load, automatically reducing switching frequency. This device incorporates burst mode operation to further improve light load performance, enabling systems to meet challenging energy standards while eliminating the need to switch off the PFC. UCC28056 can drive a PFC power stage up to 300W, providing a sinusoidal line input current with low distortion, close to unity power factor. These features along with FET drain valley turn-on with a simple boost inductor allows the lowest component count and reduced system cost.

  • Excellent light load efficiency and high efficiency over a wide range of load due to multi-mode TM and DCM control
  • Enables low system cost through FET drain valley synchronized turn-on which eliminates the need for a second winding on the boost inductor
  • Burst mode with soft-entry and soft-exit periods enables ultra-low audible noise output
  • Low start-up current consumption (< 46μA)
  • Wide VCC range 8.5V to 34V
  • Cycle-by-cycle current limit
  • Second independent OVP
  • Integrated OTP