SNAA386 November 2023 CDCE6214 , CDCE6214-Q1 , CDCE6214Q1TM , LMK00301 , LMK00304 , LMK00306 , LMK00308 , LMK00334 , LMK00334-Q1 , LMK00338 , LMK03318 , LMK03328 , LMK3H0102 , LMK6C , LMK6H , LMKDB1104 , LMKDB1108 , LMKDB1120 , LMKDB1202 , LMKDB1204
In PCIe systems, both the transmitter and receiver devices are provided with a reference clock, referred to as REFCLK. For all PCIe generations, REFCLK is a 100 MHz HCSL clock, and Table 3-1 shows the maximum frequency stability requirements by generation for Common Clock architectures.
PCIe Generation | Frequency Stability (ppm)(1) |
---|---|
PCIe 1.1 | ±300 |
PCIe 2.1 | ±300 |
PCIe 3.1 | ±300 |
PCIe 4.0 | ±300 |
PCIe 5.0 | ±100 |
PCIe 6.0 | ±100 |
The clocking architectures are as follows: