SPRADB3 October   2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between AM263 and AM263P
  5. 2Feature Differences for System Consideration
    1. 2.1 New Features in AM263P
      1. 2.1.1 Resolver Peripheral
        1. 2.1.1.1 Migration From Software to Hardware Resolver
      2. 2.1.2 Trigonometric Math Unit
      3. 2.1.3 Remote L2 Cache
    2. 2.2 Memory Subsystem Differences
    3. 2.3 CONTROLSS Module Differences
      1. 2.3.1 ADC Feature Differences and Additions
      2. 2.3.2 ADC Safety Tile Additions
      3. 2.3.3 ADC_R Module Addition
    4. 2.4 QSPI/OSPI Module Differences
    5. 2.5 Hardware Security Module Differences
    6. 2.6 Hardware Differences
      1. 2.6.1 Sourcing VPP With ANALDO
  6. 3Software Changes Between AM263 and AM263P SDK
  7. 4List of Errata Fixes in AM263P

2.1.3 Remote L2 Cache

Each R5F core for all AM263P devices now has an integrated Remote L2 (RL2) Cache controller that can be used to reserve system memory to cache data. As it uses system memory, the RAM comes with EEC protection. The memory is structured to support 4096 lines of cache support at a line size of 32 bytes. The cache lines are software programmable and can support sizes of 8, 16, 32, 64, or 128kB.

The primary use case for this feature is to cache system data that is typically stored in flash memory into the SoC memory system to improve the processing performance. As the RL2 uses system memory, there are access protections that must be configured to guard its contents so no system data is altered by mistake. For more information, see the AM263P Technical Reference Manual.