SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The interrupt router is configured without an INTD (no_intd = 1), it performs only interrupt muxing.
Table 10-99 shows the interrupt inputs listed from the higher order bits to the lower order bits.
NAVSS0_INTR_ROUTER0 Input(s) | Interrupt Mapping (MSB to LSB) |
---|---|
INRTR_IN[441] | IO_PVU0_EXP_INTR |
INRTR_IN[440] | DMA_PVU0_EXP_INTR |
INRTR_IN[439:436] | MAILBOX0_CLUSTER0_PEND_INTR[3:0] |
INRTR_IN[435:432] | MAILBOX0_CLUSTER1_PEND_INTR[3:0] |
INRTR_IN[431:428] | MAILBOX0_CLUSTER2_PEND_INTR[3:0] |
INRTR_IN[427:424] | MAILBOX0_CLUSTER3_PEND_INTR[3:0] |
INRTR_IN[423:420] | MAILBOX0_CLUSTER4_PEND_INTR[3:0] |
INRTR_IN[419:416] | MAILBOX0_CLUSTER5_PEND_INTR[3:0] |
INRTR_IN[415:412] | MAILBOX0_CLUSTER6_PEND_INTR[3:0] |
INRTR_IN[411:408] | MAILBOX0_CLUSTER7_PEND_INTR[3:0] |
INRTR_IN[407:404] | MAILBOX0_CLUSTER8_PEND_INTR[3:0] |
INRTR_IN[403:400] | MAILBOX0_CLUSTER9_PEND_INTR[3:0] |
INRTR_IN[399:396] | MAILBOX0_CLUSTER10_PEND_INTR[3:0] |
INRTR_IN[395:392] | MAILBOX0_CLUSTER11_PEND_INTR[3:0] |
INRTR_IN[391] | CPTS0_EVNT_PEND_INTR |
INRTR_IN[390] | Reserved |
INRTR_IN[389] | Reserved |
INRTR_IN[388] | MCRC0_MCRC_PEND_INTR |
INRTR_IN[387:384] | MCRC0_EVENT_PEND_INTR[3:0] |
INRTR_IN[383:320] | MODSS_INTA0_VINTR_PEND[63:0] |
INRTR_IN[319:256] | MODSS_INTA1_VINTR_PEND[63:0] |
INRTR_IN[255:0] | UDMASS_INTA0_VINTR_PEND[255:0] |
Interrupt router outputs are described in Table 10-98, NAVSS0 Hardware Requests.
Interrupt router registers are described in INTR0_INTR_ROUTER_CFG Registers.