SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 5-1578 describes the PLL SSMOD control bitfields. Figure 5-764 describes the connection between a SSMOD and a PLL.
Parameter | Register | Description |
---|---|---|
SSMOD enable control | <PLL_name>n_SS_CTRL[31](1) BYPASS_EN (For example, MCU_PLL0 - MCU_PLL0_SS_CTRL[31] BYPASS_EN) | Enable/disable the PLL SSMOD feature. |
Wave table maximum address | <PLL_name>n_SS_CTRL[25-18](1) WV_TBL_MAXADDR (For example, MCU_PLL0 - MCU_PLL0_SS_CTRL[25-18] WV_TBL_MAXADDR) | Wave table maximum address. Indicates the maximum number of address bits used to access the externalwave table. These bits are not used if <PLL_name>n_SS_CTRL[0] WAVE_SEL = 0 |
Type of spread | <PLL_name>n_SS_CTRL[4](1) DOWNSPREAD_EN (For example, MCU_PLL0 - MCU_PLL0_SS_CTRL[4] DOWNSPREAD_EN) | Selects center spread or down spread clock variance |
Wave table selection | <PLL_name>n_SS_CTRL[0] (1) WAVE_SEL (For example, MCU_PLL0 - MCU_PLL0_SS_CTRL[0] WAVE_SEL) | Wave pattern select External wave table should only be selected |
Modulation dvider | <PLL_name>n_SS_SPREAD[19-16] (1) MOD_DIV (For example, MCU_PLL0 - MCU_PLL0_SS_SPREAD[19-16] MOD_DIV) | Input clock divider. This divider sets the modulation frequency. |
Spread Depth | <PLL_name>n_SS_SPREAD[4-0] (1) SPREAD (For example, MCU_PLL0 - MCU_PLL0_SS_SPREAD[4-0] SPREAD) | Sets the spread modulation depth. |