SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The MCSPI_XFERLEVEL[7-0] AEL bit field is needed when the buffer is used to transmit an MCSPI word to a peripheral (the MCSPI_CHCONF_0/1/2/3[27] FFEW bit must be set to 1). It defines the almost-empty buffer status. See Table 12-616.
When the FIFO pointer does not reach this level, an interrupt or a DMA request is sent to the processor to enable the system to write AEL + 1 bytes to the transmit register.
AEL + 1 must correspond to a multiple value of the MCSPI_CHCONF_0/1/2/3[11-7] WL bit field.
When DMA is used, the request is de-asserted after the first transmit register write.
No new request is asserted again as long as the system has not performed the correct number of write accesses.
The MCSPI_IRQSTATUS register bits are not available in DMA mode. In DMA mode, the MCSPI_DMA_WRITE_EVENTi request is asserted on the same conditions as the MCSPI_IRQSTATUS TXx_EMPTY flag.