SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-5351 lists the memory-mapped registers for the MCAN ECC Aggregator. All register offset addresses not listed in Table 12-5351 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_MCAN0_ECC_AGGR | 4070 0000h |
MCU_MCAN1_ECC_AGGR | 4070 1000h |
MCAN0_ECC_AGGR | 02A7 8000h |
MCAN1_ECC_AGGR | 02A7 9000h |
MCAN2_ECC_AGGR | 02A7 A000h |
MCAN3_ECC_AGGR | 02A7 B000h |
MCAN4_ECC_AGGR | 02A7 C000h |
MCAN5_ECC_AGGR | 02A7 D000h |
MCAN6_ECC_AGGR | 02A7 E000h |
MCAN7_ECC_AGGR | 02A7 F000h |
MCAN8_ECC_AGGR | 02A4 0000h |
MCAN9_ECC_AGGR | 02A4 1000h |
MCAN10_ECC_AGGR | 02A4 2000h |
MCAN11_ECC_AGGR | 02A4 3000h |
MCAN12_ECC_AGGR | 02A4 4000h |
MCAN13_ECC_AGGR | 02A4 5000h |
MCAN14_ECC_AGGR | 02A4 6000h |
MCAN15_ECC_AGGR | 02A4 7000h |
MCAN16_ECC_AGGR | 02A4 8000h |
MCAN17_ECC_AGGR | 02A4 9000h |
Offset | Acronym | Register Name | MCU_MCAN0_ECC_AGGR Physical Address | MCU_MCAN1_ECC_AGGR Physical Address |
---|---|---|---|---|
0h | MCANSS_ECC_REV | Aggregator Revision Register | 4070 0000h | 4070 1000h |
8h | MCANSS_ECC_VECTOR | ECC Vector Register | 4070 0008h | 4070 1008h |
Ch | MCANSS_ECC_STAT | Misc Status Register | 4070 000Ch | 4070 100Ch |
3Ch | MCANSS_ECC_SEC_EOI_REG | SEC EOI Register | 4070 003Ch | 4070 103Ch |
40h | MCANSS_ECC_SEC_STATUS_REG0 | SEC Interrupt Status Register 0 | 4070 0040h | 4070 1040h |
80h | MCANSS_ECC_SEC_ENABLE_SET_REG0 | SEC Interrupt Enable Set Register 0 | 4070 0080h | 4070 1080h |
C0h | MCANSS_ECC_SEC_ENABLE_CLR_REG0 | SEC Interrupt Enable Clear Register 0 | 4070 00C0h | 4070 10C0h |
13Ch | MCANSS_ECC_DED_EOI_REG | DED EOI Register | 4070 013Ch | 4070 113Ch |
140h | MCANSS_ECC_DED_STATUS_REG0 | DED Interrupt Status Register 0 | 4070 0140h | 4070 1140h |
180h | MCANSS_ECC_DED_ENABLE_SET_REG0 | DED Interrupt Enable Set Register 0 | 4070 0180h | 4070 1180h |
1C0h | MCANSS_ECC_DED_ENABLE_CLR_REG0 | DED Interrupt Enable Clear Register 0 | 4070 01C0h | 4070 11C0h |
200h | MCANSS_ECC_AGGR_ENABLE_SET | Aggregator Interrupt Enable Set Register | 4070 0200h | 4070 1200h |
204h | MCANSS_ECC_AGGR_ENABLE_CLR | Aggregator Interrupt Enable Clear Register | 4070 0204h | 4070 1204h |
208h | MCANSS_ECC_AGGR_STATUS_SET | Aggregator Interrupt Status Set Register | 4070 0208h | 4070 1208h |
20Ch | MCANSS_ECC_AGGR_STATUS_CLR | Aggregator Interrupt Status Clear Register | 4070 020Ch | 4070 120Ch |
Offset | Acronym | Register Name | MCAN0_ECC_AGGR Physical Address | MCAN1_ECC_AGGR Physical Address |
---|---|---|---|---|
0h | MCANSS_ECC_REV | Aggregator Revision Register | 02A7 8000h | 02A7 9000h |
8h | MCANSS_ECC_VECTOR | ECC Vector Register | 02A7 8008h | 02A7 9008h |
Ch | MCANSS_ECC_STAT | Misc Status Register | 02A7 800Ch | 02A7 900Ch |
3Ch | MCANSS_ECC_SEC_EOI_REG | SEC EOI Register | 02A7 803Ch | 02A7 903Ch |
40h | MCANSS_ECC_SEC_STATUS_REG0 | SEC Interrupt Status Register 0 | 02A7 8040h | 02A7 9040h |
80h | MCANSS_ECC_SEC_ENABLE_SET_REG0 | SEC Interrupt Enable Set Register 0 | 02A7 8080h | 02A7 9080h |
C0h | MCANSS_ECC_SEC_ENABLE_CLR_REG0 | SEC Interrupt Enable Clear Register 0 | 02A7 80C0h | 02A7 90C0h |
13Ch | MCANSS_ECC_DED_EOI_REG | DED EOI Register | 02A7 813Ch | 02A7 913Ch |
140h | MCANSS_ECC_DED_STATUS_REG0 | DED Interrupt Status Register 0 | 02A7 8140h | 02A7 9140h |
180h | MCANSS_ECC_DED_ENABLE_SET_REG0 | DED Interrupt Enable Set Register 0 | 02A7 8180h | 02A7 9180h |
1C0h | MCANSS_ECC_DED_ENABLE_CLR_REG0 | DED Interrupt Enable Clear Register 0 | 02A7 81C0h | 02A7 91C0h |
200h | MCANSS_ECC_AGGR_ENABLE_SET | Aggregator Interrupt Enable Set Register | 02A7 8200h | 02A7 9200h |
204h | MCANSS_ECC_AGGR_ENABLE_CLR | Aggregator Interrupt Enable Clear Register | 02A7 8204h | 02A7 9204h |
208h | MCANSS_ECC_AGGR_STATUS_SET | Aggregator Interrupt Status Set Register | 02A7 8208h | 02A7 9208h |
20Ch | MCANSS_ECC_AGGR_STATUS_CLR | Aggregator Interrupt Status Clear Register | 02A7 820Ch | 02A7 920Ch |
Offset | Acronym | Register Name | MCAN2_ECC_AGGR Physical Address | MCAN3_ECC_AGGR Physical Address |
---|---|---|---|---|
0h | MCANSS_ECC_REV | Aggregator Revision Register | 02A7 A000h | 02A7 B000h |
8h | MCANSS_ECC_VECTOR | ECC Vector Register | 02A7 A008h | 02A7 B008h |
Ch | MCANSS_ECC_STAT | Misc Status Register | 02A7 A00Ch | 02A7 B00Ch |
3Ch | MCANSS_ECC_SEC_EOI_REG | SEC EOI Register | 02A7 A03Ch | 02A7 B03Ch |
40h | MCANSS_ECC_SEC_STATUS_REG0 | SEC Interrupt Status Register 0 | 02A7 A040h | 02A7 B040h |
80h | MCANSS_ECC_SEC_ENABLE_SET_REG0 | SEC Interrupt Enable Set Register 0 | 02A7 A080h | 02A7 B080h |
C0h | MCANSS_ECC_SEC_ENABLE_CLR_REG0 | SEC Interrupt Enable Clear Register 0 | 02A7 A0C0h | 02A7 B0C0h |
13Ch | MCANSS_ECC_DED_EOI_REG | DED EOI Register | 02A7 A13Ch | 02A7 B13Ch |
140h | MCANSS_ECC_DED_STATUS_REG0 | DED Interrupt Status Register 0 | 02A7 A140h | 02A7 B140h |
180h | MCANSS_ECC_DED_ENABLE_SET_REG0 | DED Interrupt Enable Set Register 0 | 02A7 A180h | 02A7 B180h |
1C0h | MCANSS_ECC_DED_ENABLE_CLR_REG0 | DED Interrupt Enable Clear Register 0 | 02A7 A1C0h | 02A7 B1C0h |
200h | MCANSS_ECC_AGGR_ENABLE_SET | Aggregator Interrupt Enable Set Register | 02A7 A200h | 02A7 B200h |
204h | MCANSS_ECC_AGGR_ENABLE_CLR | Aggregator Interrupt Enable Clear Register | 02A7 A204h | 02A7 B204h |
208h | MCANSS_ECC_AGGR_STATUS_SET | Aggregator Interrupt Status Set Register | 02A7 A208h | 02A7 B208h |
20Ch | MCANSS_ECC_AGGR_STATUS_CLR | Aggregator Interrupt Status Clear Register | 02A7 A20Ch | 02A7 B20Ch |
Offset | Acronym | Register Name | MCAN4_ECC_AGGR Physical Address | MCAN5_ECC_AGGR Physical Address |
---|---|---|---|---|
0h | MCANSS_ECC_REV | Aggregator Revision Register | 02A7 C000h | 02A7 D000h |
8h | MCANSS_ECC_VECTOR | ECC Vector Register | 02A7 C008h | 02A7 D008h |
Ch | MCANSS_ECC_STAT | Misc Status Register | 02A7 C00Ch | 02A7 D00Ch |
3Ch | MCANSS_ECC_SEC_EOI_REG | SEC EOI Register | 02A7 C03Ch | 02A7 D03Ch |
40h | MCANSS_ECC_SEC_STATUS_REG0 | SEC Interrupt Status Register 0 | 02A7 C040h | 02A7 D040h |
80h | MCANSS_ECC_SEC_ENABLE_SET_REG0 | SEC Interrupt Enable Set Register 0 | 02A7 C080h | 02A7 D080h |
C0h | MCANSS_ECC_SEC_ENABLE_CLR_REG0 | SEC Interrupt Enable Clear Register 0 | 02A7 C0C0h | 02A7 D0C0h |
13Ch | MCANSS_ECC_DED_EOI_REG | DED EOI Register | 02A7 C13Ch | 02A7 D13Ch |
140h | MCANSS_ECC_DED_STATUS_REG0 | DED Interrupt Status Register 0 | 02A7 C140h | 02A7 D140h |
180h | MCANSS_ECC_DED_ENABLE_SET_REG0 | DED Interrupt Enable Set Register 0 | 02A7 C180h | 02A7 D180h |
1C0h | MCANSS_ECC_DED_ENABLE_CLR_REG0 | DED Interrupt Enable Clear Register 0 | 02A7 C1C0h | 02A7 D1C0h |
200h | MCANSS_ECC_AGGR_ENABLE_SET | Aggregator Interrupt Enable Set Register | 02A7 C200h | 02A7 D200h |
204h | MCANSS_ECC_AGGR_ENABLE_CLR | Aggregator Interrupt Enable Clear Register | 02A7 C204h | 02A7 D204h |
208h | MCANSS_ECC_AGGR_STATUS_SET | Aggregator Interrupt Status Set Register | 02A7 C208h | 02A7 D208h |
20Ch | MCANSS_ECC_AGGR_STATUS_CLR | Aggregator Interrupt Status Clear Register | 02A7 C20Ch | 02A7 D20Ch |
Offset | Acronym | Register Name | MCAN6_ECC_AGGR Physical Address | MCAN7_ECC_AGGR Physical Address |
---|---|---|---|---|
0h | MCANSS_ECC_REV | Aggregator Revision Register | 02A7 E000h | 02A7 F000h |
8h | MCANSS_ECC_VECTOR | ECC Vector Register | 02A7 E008h | 02A7 F008h |
Ch | MCANSS_ECC_STAT | Misc Status Register | 02A7 E00Ch | 02A7 F00Ch |
3Ch | MCANSS_ECC_SEC_EOI_REG | SEC EOI Register | 02A7 E03Ch | 02A7 F03Ch |
40h | MCANSS_ECC_SEC_STATUS_REG0 | SEC Interrupt Status Register 0 | 02A7 E040h | 02A7 F040h |
80h | MCANSS_ECC_SEC_ENABLE_SET_REG0 | SEC Interrupt Enable Set Register 0 | 02A7 E080h | 02A7 F080h |
C0h | MCANSS_ECC_SEC_ENABLE_CLR_REG0 | SEC Interrupt Enable Clear Register 0 | 02A7 E0C0h | 02A7 F0C0h |
13Ch | MCANSS_ECC_DED_EOI_REG | DED EOI Register | 02A7 E13Ch | 02A7 F13Ch |
140h | MCANSS_ECC_DED_STATUS_REG0 | DED Interrupt Status Register 0 | 02A7 E140h | 02A7 F140h |
180h | MCANSS_ECC_DED_ENABLE_SET_REG0 | DED Interrupt Enable Set Register 0 | 02A7 E180h | 02A7 F180h |
1C0h | MCANSS_ECC_DED_ENABLE_CLR_REG0 | DED Interrupt Enable Clear Register 0 | 02A7 E1C0h | 02A7 F1C0h |
200h | MCANSS_ECC_AGGR_ENABLE_SET | Aggregator Interrupt Enable Set Register | 02A7 E200h | 02A7 F200h |
204h | MCANSS_ECC_AGGR_ENABLE_CLR | Aggregator Interrupt Enable Clear Register | 02A7 E204h | 02A7 F204h |
208h | MCANSS_ECC_AGGR_STATUS_SET | Aggregator Interrupt Status Set Register | 02A7 E208h | 02A7 F208h |
20Ch | MCANSS_ECC_AGGR_STATUS_CLR | Aggregator Interrupt Status Clear Register | 02A7 E20Ch | 02A7 F20Ch |
Offset | Acronym | Register Name | MCAN8_ECC_AGGR Physical Address | MCAN9_ECC_AGGR Physical Address |
---|---|---|---|---|
0h | MCANSS_ECC_REV | Aggregator Revision Register | 02A4 0000h | 02A4 1000h |
8h | MCANSS_ECC_VECTOR | ECC Vector Register | 02A4 0008h | 02A4 1008h |
Ch | MCANSS_ECC_STAT | Misc Status Register | 02A4 000Ch | 02A4 100Ch |
3Ch | MCANSS_ECC_SEC_EOI_REG | SEC EOI Register | 02A4 003Ch | 02A4 103Ch |
40h | MCANSS_ECC_SEC_STATUS_REG0 | SEC Interrupt Status Register 0 | 02A4 0040h | 02A4 1040h |
80h | MCANSS_ECC_SEC_ENABLE_SET_REG0 | SEC Interrupt Enable Set Register 0 | 02A4 0080h | 02A4 1080h |
C0h | MCANSS_ECC_SEC_ENABLE_CLR_REG0 | SEC Interrupt Enable Clear Register 0 | 02A4 00C0h | 02A4 10C0h |
13Ch | MCANSS_ECC_DED_EOI_REG | DED EOI Register | 02A4 013Ch | 02A4 113Ch |
140h | MCANSS_ECC_DED_STATUS_REG0 | DED Interrupt Status Register 0 | 02A4 0140h | 02A4 1140h |
180h | MCANSS_ECC_DED_ENABLE_SET_REG0 | DED Interrupt Enable Set Register 0 | 02A4 0180h | 02A4 1180h |
1C0h | MCANSS_ECC_DED_ENABLE_CLR_REG0 | DED Interrupt Enable Clear Register 0 | 02A4 01C0h | 02A4 11C0h |
200h | MCANSS_ECC_AGGR_ENABLE_SET | Aggregator Interrupt Enable Set Register | 02A4 0200h | 02A4 1200h |
204h | MCANSS_ECC_AGGR_ENABLE_CLR | Aggregator Interrupt Enable Clear Register | 02A4 0204h | 02A4 1204h |
208h | MCANSS_ECC_AGGR_STATUS_SET | Aggregator Interrupt Status Set Register | 02A4 0208h | 02A4 1208h |
20Ch | MCANSS_ECC_AGGR_STATUS_CLR | Aggregator Interrupt Status Clear Register | 02A4 020Ch | 02A4 120Ch |
Offset | Acronym | Register Name | MCAN10_ECC_AGGR Physical Address | MCAN11_ECC_AGGR Physical Address |
---|---|---|---|---|
0h | MCANSS_ECC_REV | Aggregator Revision Register | 02A4 2000h | 02A4 3000h |
8h | MCANSS_ECC_VECTOR | ECC Vector Register | 02A4 2008h | 02A4 3008h |
Ch | MCANSS_ECC_STAT | Misc Status Register | 02A4 200Ch | 02A4 300Ch |
3Ch | MCANSS_ECC_SEC_EOI_REG | SEC EOI Register | 02A4 203Ch | 02A4 303Ch |
40h | MCANSS_ECC_SEC_STATUS_REG0 | SEC Interrupt Status Register 0 | 02A4 2040h | 02A4 3040h |
80h | MCANSS_ECC_SEC_ENABLE_SET_REG0 | SEC Interrupt Enable Set Register 0 | 02A4 2080h | 02A4 3080h |
C0h | MCANSS_ECC_SEC_ENABLE_CLR_REG0 | SEC Interrupt Enable Clear Register 0 | 02A4 20C0h | 02A4 30C0h |
13Ch | MCANSS_ECC_DED_EOI_REG | DED EOI Register | 02A4 213Ch | 02A4 313Ch |
140h | MCANSS_ECC_DED_STATUS_REG0 | DED Interrupt Status Register 0 | 02A4 2140h | 02A4 3140h |
180h | MCANSS_ECC_DED_ENABLE_SET_REG0 | DED Interrupt Enable Set Register 0 | 02A4 2180h | 02A4 3180h |
1C0h | MCANSS_ECC_DED_ENABLE_CLR_REG0 | DED Interrupt Enable Clear Register 0 | 02A4 21C0h | 02A4 31C0h |
200h | MCANSS_ECC_AGGR_ENABLE_SET | Aggregator Interrupt Enable Set Register | 02A4 2200h | 02A4 3200h |
204h | MCANSS_ECC_AGGR_ENABLE_CLR | Aggregator Interrupt Enable Clear Register | 02A4 2204h | 02A4 3204h |
208h | MCANSS_ECC_AGGR_STATUS_SET | Aggregator Interrupt Status Set Register | 02A4 2208h | 02A4 3208h |
20Ch | MCANSS_ECC_AGGR_STATUS_CLR | Aggregator Interrupt Status Clear Register | 02A4 220Ch | 02A4 320Ch |
Offset | Acronym | Register Name | MCAN12_ECC_AGGR Physical Address | MCAN13_ECC_AGGR Physical Address |
---|---|---|---|---|
0h | MCANSS_ECC_REV | Aggregator Revision Register | 02A4 4000h | 02A4 5000h |
8h | MCANSS_ECC_VECTOR | ECC Vector Register | 02A4 4008h | 02A4 5008h |
Ch | MCANSS_ECC_STAT | Misc Status Register | 02A4 400Ch | 02A4 500Ch |
3Ch | MCANSS_ECC_SEC_EOI_REG | SEC EOI Register | 02A4 403Ch | 02A4 503Ch |
40h | MCANSS_ECC_SEC_STATUS_REG0 | SEC Interrupt Status Register 0 | 02A4 4040h | 02A4 5040h |
80h | MCANSS_ECC_SEC_ENABLE_SET_REG0 | SEC Interrupt Enable Set Register 0 | 02A4 4080h | 02A4 5080h |
C0h | MCANSS_ECC_SEC_ENABLE_CLR_REG0 | SEC Interrupt Enable Clear Register 0 | 02A4 40C0h | 02A4 50C0h |
13Ch | MCANSS_ECC_DED_EOI_REG | DED EOI Register | 02A4 413Ch | 02A4 513Ch |
140h | MCANSS_ECC_DED_STATUS_REG0 | DED Interrupt Status Register 0 | 02A4 4140h | 02A4 5140h |
180h | MCANSS_ECC_DED_ENABLE_SET_REG0 | DED Interrupt Enable Set Register 0 | 02A4 4180h | 02A4 5180h |
1C0h | MCANSS_ECC_DED_ENABLE_CLR_REG0 | DED Interrupt Enable Clear Register 0 | 02A4 41C0h | 02A4 51C0h |
200h | MCANSS_ECC_AGGR_ENABLE_SET | Aggregator Interrupt Enable Set Register | 02A4 4200h | 02A4 5200h |
204h | MCANSS_ECC_AGGR_ENABLE_CLR | Aggregator Interrupt Enable Clear Register | 02A4 4204h | 02A4 5204h |
208h | MCANSS_ECC_AGGR_STATUS_SET | Aggregator Interrupt Status Set Register | 02A4 4208h | 02A4 5208h |
20Ch | MCANSS_ECC_AGGR_STATUS_CLR | Aggregator Interrupt Status Clear Register | 02A4 420Ch | 02A4 520Ch |
Offset | Acronym | Register Name | MCAN14_ECC_AGGR Physical Address | MCAN15_ECC_AGGR Physical Address |
---|---|---|---|---|
0h | MCANSS_ECC_REV | Aggregator Revision Register | 02A4 6000h | 02A4 7000h |
8h | MCANSS_ECC_VECTOR | ECC Vector Register | 02A4 6008h | 02A4 7008h |
Ch | MCANSS_ECC_STAT | Misc Status Register | 02A4 600Ch | 02A4 700Ch |
3Ch | MCANSS_ECC_SEC_EOI_REG | SEC EOI Register | 02A4 603Ch | 02A4 703Ch |
40h | MCANSS_ECC_SEC_STATUS_REG0 | SEC Interrupt Status Register 0 | 02A4 6040h | 02A4 7040h |
80h | MCANSS_ECC_SEC_ENABLE_SET_REG0 | SEC Interrupt Enable Set Register 0 | 02A4 6080h | 02A4 7080h |
C0h | MCANSS_ECC_SEC_ENABLE_CLR_REG0 | SEC Interrupt Enable Clear Register 0 | 02A4 60C0h | 02A4 70C0h |
13Ch | MCANSS_ECC_DED_EOI_REG | DED EOI Register | 02A4 613Ch | 02A4 713Ch |
140h | MCANSS_ECC_DED_STATUS_REG0 | DED Interrupt Status Register 0 | 02A4 6140h | 02A4 7140h |
180h | MCANSS_ECC_DED_ENABLE_SET_REG0 | DED Interrupt Enable Set Register 0 | 02A4 6180h | 02A4 7180h |
1C0h | MCANSS_ECC_DED_ENABLE_CLR_REG0 | DED Interrupt Enable Clear Register 0 | 02A4 61C0h | 02A4 71C0h |
200h | MCANSS_ECC_AGGR_ENABLE_SET | Aggregator Interrupt Enable Set Register | 02A4 6200h | 02A4 7200h |
204h | MCANSS_ECC_AGGR_ENABLE_CLR | Aggregator Interrupt Enable Clear Register | 02A4 6204h | 02A4 7204h |
208h | MCANSS_ECC_AGGR_STATUS_SET | Aggregator Interrupt Status Set Register | 02A4 6208h | 02A4 7208h |
20Ch | MCANSS_ECC_AGGR_STATUS_CLR | Aggregator Interrupt Status Clear Register | 02A4 620Ch | 02A4 720Ch |
Offset | Acronym | Register Name | MCAN16_ECC_AGGR Physical Address | MCAN17_ECC_AGGR Physical Address |
---|---|---|---|---|
0h | MCANSS_ECC_REV | Aggregator Revision Register | 02A4 8000h | 02A4 9000h |
8h | MCANSS_ECC_VECTOR | ECC Vector Register | 02A4 8008h | 02A4 9008h |
Ch | MCANSS_ECC_STAT | Misc Status Register | 02A4 800Ch | 02A4 900Ch |
3Ch | MCANSS_ECC_SEC_EOI_REG | SEC EOI Register | 02A4 803Ch | 02A4 903Ch |
40h | MCANSS_ECC_SEC_STATUS_REG0 | SEC Interrupt Status Register 0 | 02A4 8040h | 02A4 9040h |
80h | MCANSS_ECC_SEC_ENABLE_SET_REG0 | SEC Interrupt Enable Set Register 0 | 02A4 8080h | 02A4 9080h |
C0h | MCANSS_ECC_SEC_ENABLE_CLR_REG0 | SEC Interrupt Enable Clear Register 0 | 02A4 80C0h | 02A4 90C0h |
13Ch | MCANSS_ECC_DED_EOI_REG | DED EOI Register | 02A4 813Ch | 02A4 913Ch |
140h | MCANSS_ECC_DED_STATUS_REG0 | DED Interrupt Status Register 0 | 02A4 8140h | 02A4 9140h |
180h | MCANSS_ECC_DED_ENABLE_SET_REG0 | DED Interrupt Enable Set Register 0 | 02A4 8180h | 02A4 9180h |
1C0h | MCANSS_ECC_DED_ENABLE_CLR_REG0 | DED Interrupt Enable Clear Register 0 | 02A4 81C0h | 02A4 91C0h |
200h | MCANSS_ECC_AGGR_ENABLE_SET | Aggregator Interrupt Enable Set Register | 02A4 8200h | 02A4 9200h |
204h | MCANSS_ECC_AGGR_ENABLE_CLR | Aggregator Interrupt Enable Clear Register | 02A4 8204h | 02A4 9204h |
208h | MCANSS_ECC_AGGR_STATUS_SET | Aggregator Interrupt Status Set Register | 02A4 8208h | 02A4 9208h |
20Ch | MCANSS_ECC_AGGR_STATUS_CLR | Aggregator Interrupt Status Clear Register | 02A4 820Ch | 02A4 920Ch |
MCANSS_ECC_REV is shown in Figure 12-2808 and described in Table 12-5362.
Return to Summary Table.
Aggregator Revision Register
The Aggregator Revision Register contains the revision parameters for the ECC Aggregator.
Instance | Physical Address |
---|---|
MCU_MCAN0_ECC_AGGR | 4070 0000h |
MCU_MCAN1_ECC_AGGR | 4070 1000h |
MCAN0_ECC_AGGR | 02A7 8000h |
MCAN1_ECC_AGGR | 02A7 9000h |
MCAN2_ECC_AGGR | 02A7 A000h |
MCAN3_ECC_AGGR | 02A7 B000h |
MCAN4_ECC_AGGR | 02A7 C000h |
MCAN5_ECC_AGGR | 02A7 D000h |
MCAN6_ECC_AGGR | 02A7 E000h |
MCAN7_ECC_AGGR | 02A7 F000h |
MCAN8_ECC_AGGR | 02A4 0000h |
MCAN9_ECC_AGGR | 02A4 1000h |
MCAN10_ECC_AGGR | 02A4 2000h |
MCAN11_ECC_AGGR | 02A4 3000h |
MCAN12_ECC_AGGR | 02A4 4000h |
MCAN13_ECC_AGGR | 02A4 5000h |
MCAN14_ECC_AGGR | 02A4 6000h |
MCAN15_ECC_AGGR | 02A4 7000h |
MCAN16_ECC_AGGR | 02A4 8000h |
MCAN17_ECC_AGGR | 02A4 9000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-6A0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-1Dh | R-2h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | Business Unit |
27-16 | MODULE_ID | R | 6A0h | Module ID |
15-11 | REVRTL | R | 1Dh | RTL Version |
10-8 | REVMAJ | R | 2h | Major Version |
7-6 | CUSTOM | R | 0h | Custom Version |
5-0 | REVMIN | R | 0h | Minor Version |
MCANSS_ECC_VECTOR is shown in Figure 12-2809 and described in Table 12-5364.
Return to Summary Table.
ECC Vector Register
Instance | Physical Address |
---|---|
MCU_MCAN0_ECC_AGGR | 4070 0008h |
MCU_MCAN1_ECC_AGGR | 4070 1008h |
MCAN0_ECC_AGGR | 02A7 8008h |
MCAN1_ECC_AGGR | 02A7 9008h |
MCAN2_ECC_AGGR | 02A7 A008h |
MCAN3_ECC_AGGR | 02A7 B008h |
MCAN4_ECC_AGGR | 02A7 C008h |
MCAN5_ECC_AGGR | 02A7 D008h |
MCAN6_ECC_AGGR | 02A7 E008h |
MCAN7_ECC_AGGR | 02A7 F008h |
MCAN8_ECC_AGGR | 02A4 0008h |
MCAN9_ECC_AGGR | 02A4 1008h |
MCAN10_ECC_AGGR | 02A4 2008h |
MCAN11_ECC_AGGR | 02A4 3008h |
MCAN12_ECC_AGGR | 02A4 4008h |
MCAN13_ECC_AGGR | 02A4 5008h |
MCAN14_ECC_AGGR | 02A4 6008h |
MCAN15_ECC_AGGR | 02A4 7008h |
MCAN16_ECC_AGGR | 02A4 8008h |
MCAN17_ECC_AGGR | 02A4 9008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R-0h | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | RD_SVBUS_DONE | R/W1C | 0h | Read Done Status to indicate if read on the serial ECC interface is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read Address |
15 | RD_SVBUS | R/W1S | 0h | Read Trigger Write 1h to trigger a read on the serial ECC interface. |
14-11 | RESERVED | R | 0h | Reserved |
10-0 | ECC_VECTOR | R/W | 0h | ECC RAM ID Value written to select the corresponding ECC RAM for control or status. |
MCANSS_ECC_STAT is shown in Figure 12-2810 and described in Table 12-5366.
Return to Summary Table.
Misc Status Register
Instance | Physical Address |
---|---|
MCU_MCAN0_ECC_AGGR | 4070 000Ch |
MCU_MCAN1_ECC_AGGR | 4070 100Ch |
MCAN0_ECC_AGGR | 02A7 800Ch |
MCAN1_ECC_AGGR | 02A7 900Ch |
MCAN2_ECC_AGGR | 02A7 A00Ch |
MCAN3_ECC_AGGR | 02A7 B00Ch |
MCAN4_ECC_AGGR | 02A7 C00Ch |
MCAN5_ECC_AGGR | 02A7 D00Ch |
MCAN6_ECC_AGGR | 02A7 E00Ch |
MCAN7_ECC_AGGR | 02A7 F00Ch |
MCAN8_ECC_AGGR | 02A4 000Ch |
MCAN9_ECC_AGGR | 02A4 100Ch |
MCAN10_ECC_AGGR | 02A4 200Ch |
MCAN11_ECC_AGGR | 02A4 300Ch |
MCAN12_ECC_AGGR | 02A4 400Ch |
MCAN13_ECC_AGGR | 02A4 500Ch |
MCAN14_ECC_AGGR | 02A4 600Ch |
MCAN15_ECC_AGGR | 02A4 700Ch |
MCAN16_ECC_AGGR | 02A4 800Ch |
MCAN17_ECC_AGGR | 02A4 900Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-0h | R-2h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10-0 | NUM_RAMS | R | 2h | Number of RAMs Indicates the number of RAMs serviced by the ECC Aggregator. |
MCANSS_ECC_SEC_EOI_REG is shown in Figure 12-2811 and described in Table 12-5368.
Return to Summary Table.
SEC EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MCU_MCAN0_ECC_AGGR | 4070 003Ch |
MCU_MCAN1_ECC_AGGR | 4070 103Ch |
MCAN0_ECC_AGGR | 02A7 803Ch |
MCAN1_ECC_AGGR | 02A7 903Ch |
MCAN2_ECC_AGGR | 02A7 A03Ch |
MCAN3_ECC_AGGR | 02A7 B03Ch |
MCAN4_ECC_AGGR | 02A7 C03Ch |
MCAN5_ECC_AGGR | 02A7 D03Ch |
MCAN6_ECC_AGGR | 02A7 E03Ch |
MCAN7_ECC_AGGR | 02A7 F03Ch |
MCAN8_ECC_AGGR | 02A4 003Ch |
MCAN9_ECC_AGGR | 02A4 103Ch |
MCAN10_ECC_AGGR | 02A4 203Ch |
MCAN11_ECC_AGGR | 02A4 303Ch |
MCAN12_ECC_AGGR | 02A4 403Ch |
MCAN13_ECC_AGGR | 02A4 503Ch |
MCAN14_ECC_AGGR | 02A4 603Ch |
MCAN15_ECC_AGGR | 02A4 703Ch |
MCAN16_ECC_AGGR | 02A4 803Ch |
MCAN17_ECC_AGGR | 02A4 903Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | Single Error Correction End Of Interrupt (SEC EOI) |
MCANSS_ECC_SEC_STATUS_REG0 is shown in Figure 12-2812 and described in Table 12-5370.
Return to Summary Table.
SEC Interrupt Status Register 0
Instance | Physical Address |
---|---|
MCU_MCAN0_ECC_AGGR | 4070 0040h |
MCU_MCAN1_ECC_AGGR | 4070 1040h |
MCAN0_ECC_AGGR | 02A7 8040h |
MCAN1_ECC_AGGR | 02A7 9040h |
MCAN2_ECC_AGGR | 02A7 A040h |
MCAN3_ECC_AGGR | 02A7 B040h |
MCAN4_ECC_AGGR | 02A7 C040h |
MCAN5_ECC_AGGR | 02A7 D040h |
MCAN6_ECC_AGGR | 02A7 E040h |
MCAN7_ECC_AGGR | 02A7 F040h |
MCAN8_ECC_AGGR | 02A4 0040h |
MCAN9_ECC_AGGR | 02A4 1040h |
MCAN10_ECC_AGGR | 02A4 2040h |
MCAN11_ECC_AGGR | 02A4 3040h |
MCAN12_ECC_AGGR | 02A4 4040h |
MCAN13_ECC_AGGR | 02A4 5040h |
MCAN14_ECC_AGGR | 02A4 6040h |
MCAN15_ECC_AGGR | 02A4 7040h |
MCAN16_ECC_AGGR | 02A4 8040h |
MCAN17_ECC_AGGR | 02A4 9040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CTRL_EDC_VBUSS_PEND | MSGMEM_PEND | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CTRL_EDC_VBUSS_PEND | R/W1S | 0h | Interrupt Pending Status for CTRL_EDC_VBUSS_PEND |
0 | MSGMEM_PEND | R/W1S | 0h | Interrupt Pending Status for MSGMEM_PEND |
MCANSS_ECC_SEC_ENABLE_SET_REG0 is shown in Figure 12-2813 and described in Table 12-5372.
Return to Summary Table.
SEC Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
MCU_MCAN0_ECC_AGGR | 4070 0080h |
MCU_MCAN1_ECC_AGGR | 4070 1080h |
MCAN0_ECC_AGGR | 02A7 8080h |
MCAN1_ECC_AGGR | 02A7 9080h |
MCAN2_ECC_AGGR | 02A7 A080h |
MCAN3_ECC_AGGR | 02A7 B080h |
MCAN4_ECC_AGGR | 02A7 C080h |
MCAN5_ECC_AGGR | 02A7 D080h |
MCAN6_ECC_AGGR | 02A7 E080h |
MCAN7_ECC_AGGR | 02A7 F080h |
MCAN8_ECC_AGGR | 02A4 0080h |
MCAN9_ECC_AGGR | 02A4 1080h |
MCAN10_ECC_AGGR | 02A4 2080h |
MCAN11_ECC_AGGR | 02A4 3080h |
MCAN12_ECC_AGGR | 02A4 4080h |
MCAN13_ECC_AGGR | 02A4 5080h |
MCAN14_ECC_AGGR | 02A4 6080h |
MCAN15_ECC_AGGR | 02A4 7080h |
MCAN16_ECC_AGGR | 02A4 8080h |
MCAN17_ECC_AGGR | 02A4 9080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CTRL_EDC_VBUSS_ENABLE_SET | MSGMEM_ENABLE_SET | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CTRL_EDC_VBUSS_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set for CTRL_EDC_VBUSS_PEND |
0 | MSGMEM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set for MSGMEM_PEND |
MCANSS_ECC_SEC_ENABLE_CLR_REG0 is shown in Figure 12-2814 and described in Table 12-5374.
Return to Summary Table.
SEC Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
MCU_MCAN0_ECC_AGGR | 4070 00C0h |
MCU_MCAN1_ECC_AGGR | 4070 10C0h |
MCAN0_ECC_AGGR | 02A7 80C0h |
MCAN1_ECC_AGGR | 02A7 90C0h |
MCAN2_ECC_AGGR | 02A7 A0C0h |
MCAN3_ECC_AGGR | 02A7 B0C0h |
MCAN4_ECC_AGGR | 02A7 C0C0h |
MCAN5_ECC_AGGR | 02A7 D0C0h |
MCAN6_ECC_AGGR | 02A7 E0C0h |
MCAN7_ECC_AGGR | 02A7 F0C0h |
MCAN8_ECC_AGGR | 02A4 00C0h |
MCAN9_ECC_AGGR | 02A4 10C0h |
MCAN10_ECC_AGGR | 02A4 20C0h |
MCAN11_ECC_AGGR | 02A4 30C0h |
MCAN12_ECC_AGGR | 02A4 40C0h |
MCAN13_ECC_AGGR | 02A4 50C0h |
MCAN14_ECC_AGGR | 02A4 60C0h |
MCAN15_ECC_AGGR | 02A4 70C0h |
MCAN16_ECC_AGGR | 02A4 80C0h |
MCAN17_ECC_AGGR | 02A4 90C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CTRL_EDC_VBUSS_ENABLE_CLR | MSGMEM_ENABLE_CLR | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CTRL_EDC_VBUSS_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND |
0 | MSGMEM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear for MSGMEM_PEND |
MCANSS_ECC_DED_EOI_REG is shown in Figure 12-2815 and described in Table 12-5376.
Return to Summary Table.
DED EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MCU_MCAN0_ECC_AGGR | 4070 013Ch |
MCU_MCAN1_ECC_AGGR | 4070 113Ch |
MCAN0_ECC_AGGR | 02A7 813Ch |
MCAN1_ECC_AGGR | 02A7 913Ch |
MCAN2_ECC_AGGR | 02A7 A13Ch |
MCAN3_ECC_AGGR | 02A7 B13Ch |
MCAN4_ECC_AGGR | 02A7 C13Ch |
MCAN5_ECC_AGGR | 02A7 D13Ch |
MCAN6_ECC_AGGR | 02A7 E13Ch |
MCAN7_ECC_AGGR | 02A7 F13Ch |
MCAN8_ECC_AGGR | 02A4 013Ch |
MCAN9_ECC_AGGR | 02A4 113Ch |
MCAN10_ECC_AGGR | 02A4 213Ch |
MCAN11_ECC_AGGR | 02A4 313Ch |
MCAN12_ECC_AGGR | 02A4 413Ch |
MCAN13_ECC_AGGR | 02A4 513Ch |
MCAN14_ECC_AGGR | 02A4 613Ch |
MCAN15_ECC_AGGR | 02A4 713Ch |
MCAN16_ECC_AGGR | 02A4 813Ch |
MCAN17_ECC_AGGR | 02A4 913Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | Double Error Correction End Of Interrupt (DED EOI) |
MCANSS_ECC_DED_STATUS_REG0 is shown in Figure 12-2816 and described in Table 12-5378.
Return to Summary Table.
DED Interrupt Status Register 0
Instance | Physical Address |
---|---|
MCU_MCAN0_ECC_AGGR | 4070 0140h |
MCU_MCAN1_ECC_AGGR | 4070 1140h |
MCAN0_ECC_AGGR | 02A7 8140h |
MCAN1_ECC_AGGR | 02A7 9140h |
MCAN2_ECC_AGGR | 02A7 A140h |
MCAN3_ECC_AGGR | 02A7 B140h |
MCAN4_ECC_AGGR | 02A7 C140h |
MCAN5_ECC_AGGR | 02A7 D140h |
MCAN6_ECC_AGGR | 02A7 E140h |
MCAN7_ECC_AGGR | 02A7 F140h |
MCAN8_ECC_AGGR | 02A4 0140h |
MCAN9_ECC_AGGR | 02A4 1140h |
MCAN10_ECC_AGGR | 02A4 2140h |
MCAN11_ECC_AGGR | 02A4 3140h |
MCAN12_ECC_AGGR | 02A4 4140h |
MCAN13_ECC_AGGR | 02A4 5140h |
MCAN14_ECC_AGGR | 02A4 6140h |
MCAN15_ECC_AGGR | 02A4 7140h |
MCAN16_ECC_AGGR | 02A4 8140h |
MCAN17_ECC_AGGR | 02A4 9140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CTRL_EDC_VBUSS_PEND | MSGMEM_PEND | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CTRL_EDC_VBUSS_PEND | R/W1S | 0h | Interrupt Pending Status for CTRL_EDC_VBUSS_PEND |
0 | MSGMEM_PEND | R/W1S | 0h | Interrupt Pending Status for MSGMEM_PEND |
MCANSS_ECC_DED_ENABLE_SET_REG0 is shown in Figure 12-2817 and described in Table 12-5380.
Return to Summary Table.
DED Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
MCU_MCAN0_ECC_AGGR | 4070 0180h |
MCU_MCAN1_ECC_AGGR | 4070 1180h |
MCAN0_ECC_AGGR | 02A7 8180h |
MCAN1_ECC_AGGR | 02A7 9180h |
MCAN2_ECC_AGGR | 02A7 A180h |
MCAN3_ECC_AGGR | 02A7 B180h |
MCAN4_ECC_AGGR | 02A7 C180h |
MCAN5_ECC_AGGR | 02A7 D180h |
MCAN6_ECC_AGGR | 02A7 E180h |
MCAN7_ECC_AGGR | 02A7 F180h |
MCAN8_ECC_AGGR | 02A4 0180h |
MCAN9_ECC_AGGR | 02A4 1180h |
MCAN10_ECC_AGGR | 02A4 2180h |
MCAN11_ECC_AGGR | 02A4 3180h |
MCAN12_ECC_AGGR | 02A4 4180h |
MCAN13_ECC_AGGR | 02A4 5180h |
MCAN14_ECC_AGGR | 02A4 6180h |
MCAN15_ECC_AGGR | 02A4 7180h |
MCAN16_ECC_AGGR | 02A4 8180h |
MCAN17_ECC_AGGR | 02A4 9180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CTRL_EDC_VBUSS_ENABLE_SET | MSGMEM_ENABLE_SET | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CTRL_EDC_VBUSS_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set for CTRL_EDC_VBUSS_PEND |
0 | MSGMEM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set for MSGMEM_PEND |
MCANSS_ECC_DED_ENABLE_CLR_REG0 is shown in Figure 12-2818 and described in Table 12-5382.
Return to Summary Table.
DED Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
MCU_MCAN0_ECC_AGGR | 4070 01C0h |
MCU_MCAN1_ECC_AGGR | 4070 11C0h |
MCAN0_ECC_AGGR | 02A7 81C0h |
MCAN1_ECC_AGGR | 02A7 91C0h |
MCAN2_ECC_AGGR | 02A7 A1C0h |
MCAN3_ECC_AGGR | 02A7 B1C0h |
MCAN4_ECC_AGGR | 02A7 C1C0h |
MCAN5_ECC_AGGR | 02A7 D1C0h |
MCAN6_ECC_AGGR | 02A7 E1C0h |
MCAN7_ECC_AGGR | 02A7 F1C0h |
MCAN8_ECC_AGGR | 02A4 01C0h |
MCAN9_ECC_AGGR | 02A4 11C0h |
MCAN10_ECC_AGGR | 02A4 21C0h |
MCAN11_ECC_AGGR | 02A4 31C0h |
MCAN12_ECC_AGGR | 02A4 41C0h |
MCAN13_ECC_AGGR | 02A4 51C0h |
MCAN14_ECC_AGGR | 02A4 61C0h |
MCAN15_ECC_AGGR | 02A4 71C0h |
MCAN16_ECC_AGGR | 02A4 81C0h |
MCAN17_ECC_AGGR | 02A4 91C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CTRL_EDC_VBUSS_ENABLE_CLR | MSGMEM_ENABLE_CLR | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CTRL_EDC_VBUSS_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear for CTRL_EDC_VBUSS_PEND |
0 | MSGMEM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear for MSGMEM_PEND |
MCANSS_ECC_AGGR_ENABLE_SET is shown in Figure 12-2819 and described in Table 12-5384.
Return to Summary Table.
Aggregator Interrupt Enable Set Register
Instance | Physical Address |
---|---|
MCU_MCAN0_ECC_AGGR | 4070 0200h |
MCU_MCAN1_ECC_AGGR | 4070 1200h |
MCAN0_ECC_AGGR | 02A7 8200h |
MCAN1_ECC_AGGR | 02A7 9200h |
MCAN2_ECC_AGGR | 02A7 A200h |
MCAN3_ECC_AGGR | 02A7 B200h |
MCAN4_ECC_AGGR | 02A7 C200h |
MCAN5_ECC_AGGR | 02A7 D200h |
MCAN6_ECC_AGGR | 02A7 E200h |
MCAN7_ECC_AGGR | 02A7 F200h |
MCAN8_ECC_AGGR | 02A4 0200h |
MCAN9_ECC_AGGR | 02A4 1200h |
MCAN10_ECC_AGGR | 02A4 2200h |
MCAN11_ECC_AGGR | 02A4 3200h |
MCAN12_ECC_AGGR | 02A4 4200h |
MCAN13_ECC_AGGR | 02A4 5200h |
MCAN14_ECC_AGGR | 02A4 6200h |
MCAN15_ECC_AGGR | 02A4 7200h |
MCAN16_ECC_AGGR | 02A4 8200h |
MCAN17_ECC_AGGR | 02A4 9200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1S | 0h | Interrupt Enable Set for Serial ECC Interface Timeout Errors |
0 | PARITY | R/W1S | 0h | Interrupt Enable Set for Parity Errors |
MCANSS_ECC_AGGR_ENABLE_CLR is shown in Figure 12-2820 and described in Table 12-5386.
Return to Summary Table.
Aggregator Interrupt Enable Clear Register
Instance | Physical Address |
---|---|
MCU_MCAN0_ECC_AGGR | 4070 0204h |
MCU_MCAN1_ECC_AGGR | 4070 1204h |
MCAN0_ECC_AGGR | 02A7 8204h |
MCAN1_ECC_AGGR | 02A7 9204h |
MCAN2_ECC_AGGR | 02A7 A204h |
MCAN3_ECC_AGGR | 02A7 B204h |
MCAN4_ECC_AGGR | 02A7 C204h |
MCAN5_ECC_AGGR | 02A7 D204h |
MCAN6_ECC_AGGR | 02A7 E204h |
MCAN7_ECC_AGGR | 02A7 F204h |
MCAN8_ECC_AGGR | 02A4 0204h |
MCAN9_ECC_AGGR | 02A4 1204h |
MCAN10_ECC_AGGR | 02A4 2204h |
MCAN11_ECC_AGGR | 02A4 3204h |
MCAN12_ECC_AGGR | 02A4 4204h |
MCAN13_ECC_AGGR | 02A4 5204h |
MCAN14_ECC_AGGR | 02A4 6204h |
MCAN15_ECC_AGGR | 02A4 7204h |
MCAN16_ECC_AGGR | 02A4 8204h |
MCAN17_ECC_AGGR | 02A4 9204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1C | 0h | Interrupt Enable Clear for Serial ECC Interface Timeout Errors |
0 | PARITY | R/W1C | 0h | Interrupt Enable Clear for Parity Errors |
MCANSS_ECC_AGGR_STATUS_SET is shown in Figure 12-2821 and described in Table 12-5388.
Return to Summary Table.
Aggregator Interrupt Status Set Register
Instance | Physical Address |
---|---|
MCU_MCAN0_ECC_AGGR | 4070 0208h |
MCU_MCAN1_ECC_AGGR | 4070 1208h |
MCAN0_ECC_AGGR | 02A7 8208h |
MCAN1_ECC_AGGR | 02A7 9208h |
MCAN2_ECC_AGGR | 02A7 A208h |
MCAN3_ECC_AGGR | 02A7 B208h |
MCAN4_ECC_AGGR | 02A7 C208h |
MCAN5_ECC_AGGR | 02A7 D208h |
MCAN6_ECC_AGGR | 02A7 E208h |
MCAN7_ECC_AGGR | 02A7 F208h |
MCAN8_ECC_AGGR | 02A4 0208h |
MCAN9_ECC_AGGR | 02A4 1208h |
MCAN10_ECC_AGGR | 02A4 2208h |
MCAN11_ECC_AGGR | 02A4 3208h |
MCAN12_ECC_AGGR | 02A4 4208h |
MCAN13_ECC_AGGR | 02A4 5208h |
MCAN14_ECC_AGGR | 02A4 6208h |
MCAN15_ECC_AGGR | 02A4 7208h |
MCAN16_ECC_AGGR | 02A4 8208h |
MCAN17_ECC_AGGR | 02A4 9208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wincr-0h | R/Wincr-0h | |||||
LEGEND: R = Read Only; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wincr | 0h | Interrupt Status Set for Serial ECC Interface Timeout Errors |
1-0 | PARITY | R/Wincr | 0h | Interrupt Status Set for Parity Errors |
MCANSS_ECC_AGGR_STATUS_CLR is shown in Figure 12-2822 and described in Table 12-5390.
Return to Summary Table.
Aggregator Interrupt Status Clear Register
Instance | Physical Address |
---|---|
MCU_MCAN0_ECC_AGGR | 4070 020Ch |
MCU_MCAN1_ECC_AGGR | 4070 120Ch |
MCAN0_ECC_AGGR | 02A7 820Ch |
MCAN1_ECC_AGGR | 02A7 920Ch |
MCAN2_ECC_AGGR | 02A7 A20Ch |
MCAN3_ECC_AGGR | 02A7 B20Ch |
MCAN4_ECC_AGGR | 02A7 C20Ch |
MCAN5_ECC_AGGR | 02A7 D20Ch |
MCAN6_ECC_AGGR | 02A7 E20Ch |
MCAN7_ECC_AGGR | 02A7 F20Ch |
MCAN8_ECC_AGGR | 02A4 020Ch |
MCAN9_ECC_AGGR | 02A4 120Ch |
MCAN10_ECC_AGGR | 02A4 220Ch |
MCAN11_ECC_AGGR | 02A4 320Ch |
MCAN12_ECC_AGGR | 02A4 420Ch |
MCAN13_ECC_AGGR | 02A4 520Ch |
MCAN14_ECC_AGGR | 02A4 620Ch |
MCAN15_ECC_AGGR | 02A4 720Ch |
MCAN16_ECC_AGGR | 02A4 820Ch |
MCAN17_ECC_AGGR | 02A4 920Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wdecr-0h | R/Wdecr-0h | |||||
LEGEND: R = Read Only; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wdecr | 0h | Interrupt Status Clear for Serial ECC Interface Timeout Errors |
1-0 | PARITY | R/Wdecr | 0h | Interrupt Status Clear for Parity Errors |