SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-5606 lists the memory-mapped registers for the DCC registers. All register offset addresses not listed in Table 12-5606 through Table 12-5609 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
DCC0 | 0080 0000h |
DCC1 | 0080 4000h |
DCC2 | 0080 8000h |
DCC3 | 0080 C000h |
DCC4 | 0081 0000h |
DCC5 | 0081 4000h |
DCC6 | 0081 8000h |
MCU_DCC0 | 4010 0000h |
MCU_DCC1 | 4011 0000h |
MCU_DCC2 | 4012 0000h |
Offset | Acronym | Register Name | DCC0 Physical Address | DCC1 Physical Address | DCC2 Physical Address |
---|---|---|---|---|---|
0h | DCC_GCTRL | DCC Global Control Register | 0080 0000h | 0080 4000h | 0080 8000h |
4h | DCC_REV | DCC Revision ID | 0080 0004h | 0080 4004h | 0080 8004h |
8h | DCC_CNTSEED0 | Count0 Seed Value Register | 0080 0008h | 0080 4008h | 0080 8008h |
Ch | DCC_VALIDSEED0 | Valid0 Seed Value Register | 0080 000Ch | 0080 400Ch | 0080 800Ch |
10h | DCC_CNTSEED1 | Count1 Seed Value Register | 0080 0010h | 0080 4010h | 0080 8010h |
14h | DCC_STATUS | DCC Status Register | 0080 0014h | 0080 4014h | 0080 8014h |
18h | DCC_CNT0 | Count0 Value Register | 0080 0018h | 0080 4018h | 0080 8018h |
1Ch | DCC_VALID0 | Valid0 Value Register | 0080 001Ch | 0080 401Ch | 0080 801Ch |
20h | DCC_CNT1 | Count1 Value Register | 0080 0020h | 0080 4020h | 0080 8020h |
24h | DCC_CLKSRC1 | Clock Source Selection Register 1 | 0080 0024h | 0080 4024h | 0080 8024h |
28h | DCC_CLKSRC0 | Clock Source Selection Register 0 | 0080 0028h | 0080 4028h | 0080 8028h |
2Ch | DCC_GCTRL2 | DCC Global Control Register 2 | 0080 002Ch | 0080 402Ch | 0080 802Ch |
30h | DCC_STATUS2 | DCC FIFO Status Register | 0080 0030h | 0080 4030h | 0080 8030h |
34h | DCC_ERRCNT | Error Count Register | 0080 0034h | 0080 4034h | 0080 8034h |
Offset | Acronym | Register Name | DCC3 Physical Address | DCC4 Physical Address | DCC5 Physical Address |
---|---|---|---|---|---|
0h | DCC_GCTRL | DCC Global Control Register | 0080 C000h | 0081 0000h | 0081 4000h |
4h | DCC_REV | DCC Revision ID | 0080 C004h | 0081 0004h | 0081 4004h |
8h | DCC_CNTSEED0 | Count0 Seed Value Register | 0080 C008h | 0081 0008h | 0081 4008h |
Ch | DCC_VALIDSEED0 | Valid0 Seed Value Register | 0080 C00Ch | 0081 000Ch | 0081 400Ch |
10h | DCC_CNTSEED1 | Count1 Seed Value Register | 0080 C010h | 0081 0010h | 0081 4010h |
14h | DCC_STATUS | DCC Status Register | 0080 C014h | 0081 0014h | 0081 4014h |
18h | DCC_CNT0 | Count0 Value Register | 0080 C018h | 0081 0018h | 0081 4018h |
1Ch | DCC_VALID0 | Valid0 Value Register | 0080 C01Ch | 0081 001Ch | 0081 401Ch |
20h | DCC_CNT1 | Count1 Value Register | 0080 C020h | 0081 0020h | 0081 4020h |
24h | DCC_CLKSRC1 | Clock Source Selection Register 1 | 0080 C024h | 0081 0024h | 0081 4024h |
28h | DCC_CLKSRC0 | Clock Source Selection Register 0 | 0080 C028h | 0081 0028h | 0081 4028h |
2Ch | DCC_GCTRL2 | DCC Global Control Register 2 | 0080 C02Ch | 0081 002Ch | 0081 402Ch |
30h | DCC_STATUS2 | DCC FIFO Status Register | 0080 C030h | 0081 0030h | 0081 4030h |
34h | DCC_ERRCNT | Error Count Register | 0080 C034h | 0081 0034h | 0081 4034h |
Offset | Acronym | Register Name | DCC6 Physical Address |
---|---|---|---|
0h | DCC_GCTRL | DCC Global Control Register | 0081 8000h |
4h | DCC_REV | DCC Revision ID | 0081 8004h |
8h | DCC_CNTSEED0 | Count0 Seed Value Register | 0081 8008h |
Ch | DCC_VALIDSEED0 | Valid0 Seed Value Register | 0081 800Ch |
10h | DCC_CNTSEED1 | Count1 Seed Value Register | 0081 8010h |
14h | DCC_STATUS | DCC Status Register | 0081 8014h |
18h | DCC_CNT0 | Count0 Value Register | 0081 8018h |
1Ch | DCC_VALID0 | Valid0 Value Register | 0081 801Ch |
20h | DCC_CNT1 | Count1 Value Register | 0081 8020h |
24h | DCC_CLKSRC1 | Clock Source Selection Register 1 | 0081 8024h |
28h | DCC_CLKSRC0 | Clock Source Selection Register 0 | 0081 8028h |
2Ch | DCC_GCTRL2 | DCC Global Control Register 2 | 0081 802Ch |
30h | DCC_STATUS2 | DCC FIFO Status Register | 0081 8030h |
34h | DCC_ERRCNT | Error Count Register | 0081 8034h |
Offset | Acronym | Register Name | MCU_DCC0 Physical Address | MCU_DCC1 Physical Address | MCU_DCC2 Physical Address |
---|---|---|---|---|---|
0h | DCC_GCTRL | DCC Global Control Register | 4010 0000h | 4011 0000h | 4012 0000h |
4h | DCC_REV | DCC Revision ID | 4010 0004h | 4011 0004h | 4012 0004h |
8h | DCC_CNTSEED0 | Count0 Seed Value Register | 4010 0008h | 4011 0008h | 4012 0008h |
Ch | DCC_VALIDSEED0 | Valid0 Seed Value Register | 4010 000Ch | 4011 000Ch | 4012 000Ch |
10h | DCC_CNTSEED1 | Count1 Seed Value Register | 4010 0010h | 4011 0010h | 4012 0010h |
14h | DCC_STATUS | DCC Status Register | 4010 0014h | 4011 0014h | 4012 0014h |
18h | DCC_CNT0 | Count0 Value Register | 4010 0018h | 4011 0018h | 4012 0018h |
1Ch | DCC_VALID0 | Valid0 Value Register | 4010 001Ch | 4011 001Ch | 4012 001Ch |
20h | DCC_CNT1 | Count1 Value Register | 4010 0020h | 4011 0020h | 4012 0020h |
24h | DCC_CLKSRC1 | Clock Source Selection Register 1 | 4010 0024h | 4011 0024h | 4012 0024h |
28h | DCC_CLKSRC0 | Clock Source Selection Register 0 | 4010 0028h | 4011 0028h | 4012 0028h |
2Ch | DCC_GCTRL2 | DCC Global Control Register 2 | 4010 002Ch | 4011 002Ch | 4012 002Ch |
30h | DCC_STATUS2 | DCC FIFO Status Register | 4010 0030h | 4011 0030h | 4012 0030h |
34h | DCC_ERRCNT | Error Count Register | 4010 0034h | 4011 0034h | 4012 0034h |
DCC_GCTRL is shown in Figure 12-2929 and described in Table 12-5611.
Return to Summary Table.
Starts / stops the counters. Clears the error signal.
Instance | Physical Address |
---|---|
DCC0 | 0080 0000h |
DCC1 | 0080 4000h |
DCC2 | 0080 8000h |
DCC3 | 0080 C000h |
DCC4 | 0081 0000h |
DCC5 | 0081 4000h |
DCC6 | 0081 8000h |
MCU_DCC0 | 4010 0000h |
MCU_DCC1 | 4011 0000h |
MCU_DCC2 | 4012 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DONEENA | SINGLESHOT | ERRENA | DCCENA | ||||||||||||
R/W-5h | R/W-5h | R/W-5h | R/W-5h | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-12 | DONEENA | R/W | 5h | The DONEENA bit enables/disables the done interrupt signal, but has no effect on the done status flag in DCC_STAT register. |
11-8 | SINGLESHOT | R/W | 5h | The SINGLESHOT bit enables/disables repetitive operation of the DCC. |
7-4 | ERRENA | R/W | 5h | The ERRENA bit enables/disables the error signal. |
3-0 | DCCENA | R/W | 5h | The DCCENA bit starts and stops the operation of the dcc. |
DCC_REV is shown in Figure 12-2930 and described in Table 12-5613.
Return to Summary Table.
Specifies the module version.
Instance | Physical Address |
---|---|
DCC0 | 0080 0004h |
DCC1 | 0080 4004h |
DCC2 | 0080 8004h |
DCC3 | 0080 C004h |
DCC4 | 0081 0004h |
DCC5 | 0081 4004h |
DCC6 | 0081 8004h |
MCU_DCC0 | 4010 0004h |
MCU_DCC1 | 4011 0004h |
MCU_DCC2 | 4012 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
SCHEME | RESERVED | FUNC | |||||
R-1h | R-X | R-1h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FUNC | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RTL | MAJOR | ||||||
R-0h | R-3h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CUSTOM | MINOR | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | User, privilege, and debug mode (read): Returns 01. |
29-28 | RESERVED | R | X | |
27-16 | FUNC | R | 1h | Reflects software-compatability. |
15-11 | RTL | R | 0h | Incremented for releases due to spec changes or post-release design changes. |
10-8 | MAJOR | R | 3h | Represents major changes to the module (e.g. |
7-6 | CUSTOM | R | 0h | Indicates a special version of the module. |
5-0 | MINOR | R | 0h | Represents minor changes to the module (e.g. |
DCC_CNTSEED0 is shown in Figure 12-2931 and described in Table 12-5615.
Return to Summary Table.
Seed value for the counter attached to clock source 0
Instance | Physical Address |
---|---|
DCC0 | 0080 0008h |
DCC1 | 0080 4008h |
DCC2 | 0080 8008h |
DCC3 | 0080 C008h |
DCC4 | 0081 0008h |
DCC5 | 0081 4008h |
DCC6 | 0081 8008h |
MCU_DCC0 | 4010 0008h |
MCU_DCC1 | 4011 0008h |
MCU_DCC2 | 4012 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNTSEED0 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | X | |
19-0 | COUNTSEED0 | R/W | 0h | This field contains the seed value that gets loaded into counter 0 (clock source 0). |
DCC_VALIDSEED0 is shown in Figure 12-2932 and described in Table 12-5617.
Return to Summary Table.
Seed value for the timeout counter attached to clock source 0.
Instance | Physical Address |
---|---|
DCC0 | 0080 000Ch |
DCC1 | 0080 400Ch |
DCC2 | 0080 800Ch |
DCC3 | 0080 C00Ch |
DCC4 | 0081 000Ch |
DCC5 | 0081 400Ch |
DCC6 | 0081 800Ch |
MCU_DCC0 | 4010 000Ch |
MCU_DCC1 | 4011 000Ch |
MCU_DCC2 | 4012 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VALIDSEED0 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | VALIDSEED0 | R/W | 0h | This field contains the seed value that gets loaded into the valid duration counter for clock source 0. |
DCC_CNTSEED1 is shown in Figure 12-2933 and described in Table 12-5619.
Return to Summary Table.
Seed value for the counter attached to clock source 1.
Instance | Physical Address |
---|---|
DCC0 | 0080 0010h |
DCC1 | 0080 4010h |
DCC2 | 0080 8010h |
DCC3 | 0080 C010h |
DCC4 | 0081 0010h |
DCC5 | 0081 4010h |
DCC6 | 0081 8010h |
MCU_DCC0 | 4010 0010h |
MCU_DCC1 | 4011 0010h |
MCU_DCC2 | 4012 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNTSEED1 | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R/W | X | |
19-0 | COUNTSEED1 | R/W | 0h | This field contains the seed value that gets loaded into counter 1 (clock source 1). |
DCCSTATUS is shown in Figure 12-2934 and described in Table 12-5621.
Return to Summary Table.
Specifies the status of the DCC Module.
Instance | Physical Address |
---|---|
DCC0 | 0080 0014h |
DCC1 | 0080 4014h |
DCC2 | 0080 8014h |
DCC3 | 0080 C014h |
DCC4 | 0081 0014h |
DCC5 | 0081 4014h |
DCC6 | 0081 8014h |
MCU_DCC0 | 4010 0014h |
MCU_DCC1 | 4011 0014h |
MCU_DCC2 | 4012 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DONE | ERR | |||||
R/W-X | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | DONE | R/W1C | 0h | Indicates when single-shot mode is complete without error. |
0 | ERR | R/W1C | 0h | Indicates whether or not an error has occured. |
DCC_CNT0 is shown in Figure 12-2935 and described in Table 12-5623.
Return to Summary Table.
Value of the counter attached to clock source 0.
Instance | Physical Address |
---|---|
DCC0 | 0080 0018h |
DCC1 | 0080 4018h |
DCC2 | 0080 8018h |
DCC3 | 0080 C018h |
DCC4 | 0081 0018h |
DCC5 | 0081 4018h |
DCC6 | 0081 8018h |
MCU_DCC0 | 4010 0018h |
MCU_DCC1 | 4011 0018h |
MCU_DCC2 | 4012 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT0 | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | X | |
19-0 | COUNT0 | R | 0h | This field contains the current value of counter 0. |
DCC_VALID0 is shown in Figure 12-2936 and described in Table 12-5625.
Return to Summary Table.
Value of the valid counter attached to clock source 0.
Instance | Physical Address |
---|---|
DCC0 | 0080 001Ch |
DCC1 | 0080 401Ch |
DCC2 | 0080 801Ch |
DCC3 | 0080 C01Ch |
DCC4 | 0081 001Ch |
DCC5 | 0081 401Ch |
DCC6 | 0081 801Ch |
MCU_DCC0 | 4010 001Ch |
MCU_DCC1 | 4011 001Ch |
MCU_DCC2 | 4012 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VALID0 | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-0 | VALID0 | R | 0h | This field contains the current value of valid counter 0. |
DCC_CNT1 is shown in Figure 12-2937 and described in Table 12-5627.
Return to Summary Table.
Value of the counter attached to clock source 1.
Instance | Physical Address |
---|---|
DCC0 | 0080 0020h |
DCC1 | 0080 4020h |
DCC2 | 0080 8020h |
DCC3 | 0080 C020h |
DCC4 | 0081 0020h |
DCC5 | 0081 4020h |
DCC6 | 0081 8020h |
MCU_DCC0 | 4010 0020h |
MCU_DCC1 | 4011 0020h |
MCU_DCC2 | 4012 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT1 | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | X | |
19-0 | COUNT1 | R | 0h | This field contains the current value of counter 1. |
DCC_CLKSRC1 is shown in Figure 12-2938 and described in Table 12-5629.
Return to Summary Table.
Selects the clock source for counter 1.
Instance | Physical Address |
---|---|
DCC0 | 0080 0024h |
DCC1 | 0080 4024h |
DCC2 | 0080 8024h |
DCC3 | 0080 C024h |
DCC4 | 0081 0024h |
DCC5 | 0081 4024h |
DCC6 | 0081 8024h |
MCU_DCC0 | 4010 0024h |
MCU_DCC1 | 4011 0024h |
MCU_DCC2 | 4012 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY | RESERVED | CLKSRC1 | |||||||||||||
R/W-0h | R/W-X | R/W-0h | |||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-12 | KEY | R/W | 0h | This field enables or disables clock source selection for counter 1. |
11-5 | RESERVED | R/W | X | |
4-0 | CLKSRC1 | R/W | 0h | This field specifies the clock source for counter 1, when the KEY field enables this feature. |
DCC_CLKSRC0 is shown in Figure 12-2939 and described in Table 12-5631.
Return to Summary Table.
Selects the clock source for counter 0.
Instance | Physical Address |
---|---|
DCC0 | 0080 0028h |
DCC1 | 0080 4028h |
DCC2 | 0080 8028h |
DCC3 | 0080 C028h |
DCC4 | 0081 0028h |
DCC5 | 0081 4028h |
DCC6 | 0081 8028h |
MCU_DCC0 | 4010 0028h |
MCU_DCC1 | 4011 0028h |
MCU_DCC2 | 4012 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
KEY | RESERVED | CLKSRC0 | |||||||||||||
R/W-0h | R/W-X | R/W-0h | |||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-12 | KEY | R/W | 0h | This field enables or disables clock source selection for counter 0. |
11-4 | RESERVED | R/W | X | |
3-0 | CLKSRC0 | R/W | 0h | This field specifies the clock source for counter 0. |
DCC_GCTRL2 is shown in Figure 12-2940 and described in Table 12-5633.
Return to Summary Table.
Allows configuring different modes of operation for DCC.
Instance | Physical Address |
---|---|
DCC0 | 0080 002Ch |
DCC1 | 0080 402Ch |
DCC2 | 0080 802Ch |
DCC3 | 0080 C02Ch |
DCC4 | 0081 002Ch |
DCC5 | 0081 402Ch |
DCC6 | 0081 802Ch |
MCU_DCC0 | 4010 002Ch |
MCU_DCC1 | 4011 002Ch |
MCU_DCC2 | 4012 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FIFO_NONERR | FIFO_READ | CONT_ON_ERR | ||||||||||||
R/W-X | R/W-5h | R/W-5h | R/W-5h | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R/W | X | |
11-8 | FIFO_NONERR | R/W | 5h | Enables/disables FIFO writes without the error event on completion of comparison window. |
7-4 | FIFO_READ | R/W | 5h | Enables the counter read registers reflect FIFO output instead of the live counter value. |
3-0 | CONT_ON_ERR | R/W | 5h | Continues to next window of comparison despite the error condition. |
DCC_STATUS2 is shown in Figure 12-2941 and described in Table 12-5635.
Return to Summary Table.
Specifies the status of the DCC FIFOs.
Instance | Physical Address |
---|---|
DCC0 | 0080 0030h |
DCC1 | 0080 4030h |
DCC2 | 0080 8030h |
DCC3 | 0080 C030h |
DCC4 | 0081 0030h |
DCC5 | 0081 4030h |
DCC6 | 0081 8030h |
MCU_DCC0 | 4010 0030h |
MCU_DCC1 | 4011 0030h |
MCU_DCC2 | 4012 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT1_FIFO_FULL | VALID0_FIFO_FULL | COUNT0_FIFO_FULL | COUNT1_FIFO_EMPTY | VALID0_FIFO_EMPTY | COUNT0_FIFO_EMPTY | |
R-X | R-0h | R-0h | R-0h | R-1h | R-1h | R-1h | |
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | X | |
5 | COUNT1_FIFO_FULL | R | 0h | Count1 FIFO Full. |
4 | VALID0_FIFO_FULL | R | 0h | Valid0 FIFO Full. |
3 | COUNT0_FIFO_FULL | R | 0h | Count0 FIFO Full. |
2 | COUNT1_FIFO_EMPTY | R | 1h | Count1 FIFO Empty. |
1 | VALID0_FIFO_EMPTY | R | 1h | Valid0 FIFO Empty. |
0 | COUNT0_FIFO_EMPTY | R | 1h | Count0 FIFO Empty. |
DCC_ERRCNT is shown in Figure 12-2942 and described in Table 12-5637.
Return to Summary Table.
Counts number of errors since last clear.
Instance | Physical Address |
---|---|
DCC0 | 0080 0034h |
DCC1 | 0080 4034h |
DCC2 | 0080 8034h |
DCC3 | 0080 C034h |
DCC4 | 0081 0034h |
DCC5 | 0081 4034h |
DCC6 | 0081 8034h |
MCU_DCC0 | 4010 0034h |
MCU_DCC1 | 4011 0034h |
MCU_DCC2 | 4012 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ERRCNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | X | |
9-0 | ERRCNT | R/W | 0h | Counts the number of errors after the last write to this register or reset. |