SPRUJA1 October   2023

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Key Features
      1. 2.2.1 Processor
      2. 2.2.2 Power Supply
      3. 2.2.3 Memory
      4. 2.2.4 JTAG/Emulator
      5. 2.2.5 Support Interfaces and Peripherals
      6. 2.2.6 Expansion Connectors/Headers
    3. 2.3  Interface Mapping
    4. 2.4  Power ON/OFF Procedure
      1. 2.4.1 Power ON Procedure
      2. 2.4.2 Power OFF Procedure
      3. 2.4.3 Power Test Points
    5. 2.5  Clocking
      1. 2.5.1 Peripheral Ref Clock
    6. 2.6  Reset
    7. 2.7  CSI Interface
    8. 2.8  Audio Codec Interface
    9. 2.9  HDMI Display Interface
    10. 2.10 JTAG Interface
    11. 2.11 Test Automation Header
    12. 2.12 UART Interface
    13. 2.13 USB Interface
      1. 2.13.1 USB 2.0 Type A Interface
      2. 2.13.2 USB 2.0 Type C Interface
    14. 2.14 Memory Interfaces
      1. 2.14.1 OSPI Interface
      2. 2.14.2 MMC Interfaces
        1. 2.14.2.1 MMC0 - eMMC Interface
        2. 2.14.2.2 MMC1 - Micro SD Interface
        3. 2.14.2.3 MMC2 - M.2 Key E Interface
      3. 2.14.3 Board ID EEPROM
    15. 2.15 Ethernet Interface
      1. 2.15.1 CPSW Ethernet PHY 1 Default Configuration
      2. 2.15.2 CPSW Ethernet PHY 2 Default Configuration
    16. 2.16 GPIO Port Expander
    17. 2.17 GPIO Mapping
    18. 2.18 OLDI Display Interface
    19. 2.19 Power
      1. 2.19.1 Power Requirements
      2. 2.19.2 Power Input
      3. 2.19.3 Power Supply
      4. 2.19.4 Power Sequencing
      5. 2.19.5 AM62x SIP SoC Power
      6. 2.19.6 Current Monitoring
    20. 2.20 EVM User Setup/Configuration
      1. 2.20.1 EVM DIP Switches
      2. 2.20.2 Boot Modes
      3. 2.20.3 User Test LEDs
    21. 2.21 Expansion Headers
      1. 2.21.1 PRU Connector
      2. 2.21.2 User Expansion Connector
      3. 2.21.3 MCU Connector
    22. 2.22 Interrupt
    23. 2.23 I2C Address Mapping
  8. 3Hardware Design Files
  9. 4Compliance Information
    1. 4.1 Compliance and Certifications
  10. 5Additional Information
    1. 5.1 Trademarks

PRU Connector

AM62x SIP SK EVM has a 20 pin PRU Header which offers Low speed connection to the PRG0 Interface.

PRU_ICSSG signals from PRG0 Port (PRG0_PRU0) are connected to a 10x2 standard 0.1” spaced Receptacle connector Mfr Part # PREC010DAAN-RC. The connector features PR0_PRU0_GPO [0: 7], SoC_I2C0, +3.3V PWR and Ground reference. INTn signal from PRU Header is wired along with the CPSW PHY interrupts and connected to the EXTINTn pin of the SoC.

The 3.3V supply is current limited to 500 mA. This is achieved by using load switch TPS22902YFPR. Enable for the load switch is controlled by IO expander. Signals routed from the PRU Connector are listed in the table below.

GUID-20231006-SS0I-DTJF-JG7Z-6WZ5R6P8S1J6-low.png Figure 2-28 PRU Header (J10) Pin-Out
Pin Number SoC Ball No. Netname

Pin Multiplexed Signal

1 - VCC3V3_PRU
2 - DGND
3 - PRU_DETECT
4 F22 PRU_RESETz RESETSTATz
5 D16 PRU_INTn EXTINTn/ GPIO1_31
6 B16 SoC_I2C0_SCL I2C0_SCL/PR0_IEP0_EDIO_DATA_IN_OUT30/ SYNC0_OUT/ OBSCLK0/ UART1_DCDn/ EQEP2_A EHRPWM_SOCA/ GPIO1_26/ ECAP1_IN_APWM_OUT / SPI2_CS0
7 - NC
8 A16 SoC_I2C0_SDA I2C0_SDA/PR0_IEP0_EDIO_DATA_IN_OUT31/ SPI2_CS2/ TIMER_IO5/ UART1_DSRn/ EQEP2_B/ EHRPWM_SOCB/ GPIO1_27/ ECAP2_IN_APWM_OUT
9 NC
10 - NC
11 - NC
12 - NC
13 M25 PR0_PRU0_GPO0 GPMC0_AD0/ PR0_PRU1_GPO8/ PR0_PRU1_GPI8/ MCASP2_AXR4/ PR0_PRU0_GPO0/PR0_PRU0_GPI0/ TRC_CLK/ GPIO0_15/ DDR0_IO_PLL_TESTOUT0P/ DDR0_IO_PLL_TESTOUT1P/ GPIO1_112/ LED_DIO0
14 N23 PR0_PRU0_GPO1 GPMC0_AD1/ PR0_PRU1_GPO9/ PR0_PRU1_GPI9/ MCASP2_AXR5/ PR0_PRU0_GPO1/PR0_PRU0_GPI1/ TRC_CTL/ GPIO0_16/ DDR0_IO_PLL_REFCLK_TEST0P/ DDR0_IO_PLL_REFCLK_TEST1P/ GPIO1_113/ LED_DIO1
15 N24 PR0_PRU0_GPO2 GPMC0_AD2/ PR0_PRU1_GPO10/ PR0_PRU1_GPI10/ MCASP2_AXR6/PR0_PRU0_GPO2/ PR0_PRU0_GPI2/ TRC_DATA0/ GPIO0_17
16 N25 PR0_PRU0_GPO3 GPMC0_AD3/PR0_PRU1_GPO11/PR0_PRU1_GPI11/MCASP2_AXR7/PR0_PRU0_GPO3/ PR0_PRU0_GPI3/TRC_DATA1/GPIO0_18
17 P24 PR0_PRU0_GPO4 GPMC0_AD4/PR0_PRU1_GPO12/PR0_PRU1_GPI12/MCASP2_AXR8/PR0_PRU0_GPO4/PR0_PRU0_GPI4/TRC_DATA2/GPIO0_19
18 P22 PR0_PRU0_GPO5 GPMC0_AD5/PR0_PRU1_GPO13/PR0_PRU1_GPI13/MCASP2_AXR9/PR0_PRU0_GPO5/PR0_PRU0_GPI5/TRC_DATA3/GPIO0_20
19 P21 PR0_PRU0_GPO6 GPMC0_AD6/PR0_PRU1_GPO14/PR0_PRU1_GPI14/MCASP2_AXR10/PR0_PRU0_GPO6/PR0_PRU0_GPI6/TRC_DATA4/GPIO0_21
20 R23 PR0_PRU0_GPO7 GPMC0_AD7/PR0_PRU1_GPO15/PR0_PRU1_GPI15/MCASP2_AXR11/PR0_PRU0_GPO7/ PR0_PRU0_GPI7/TRC_DATA5/GPIO0_22