TIDUF35 june   2023 AM6442

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Terminology
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1  AM6442 Microprocessor
      2. 2.3.2  DP83867 gigabit Ethernet Physical Transceiver
      3. 2.3.3  DP83TD510E Single-Pair Ethernet Physical Transceiver
      4. 2.3.4  MSPM0G1107 Microcontroller
      5. 2.3.5  LMK1C1106 6-Channel Output LVCMOS 1.8-V Buffer
      6. 2.3.6  LMK6C Low-Jitter, High-Performance, Bulk-Acoustic-Wave (BAW) Fixed-Frequency LVCMOS Oscillator
      7. 2.3.7  TLVM13630 High-Density, 3-V to 36-V Input, 1-V to 6-V Output, 3-A Step-Down Power Module
      8. 2.3.8  LM74700-Q1 Reverse-Polarity Protection Ideal Diode
      9. 2.3.9  TPS62825A Synchronous Step-Down DC-DC Converter
      10. 2.3.10 LMR36006 Ultra-Small Synchronous Step-Down Converter
      11. 2.3.11 TLV62568A High-Efficiency Step-Down Buck Converter With Forced PWM
  9. 3System Design Theory
    1. 3.1 Power Subsystem
    2. 3.2 AM6442 System on Module Subsystem
    3. 3.3 Ethernet Subsystem
    4. 3.4 Power Over Data Line (PoDL) Subsystem
    5. 3.5 Additional Subsystems
      1. 3.5.1 USB 3.1 Interface
      2. 3.5.2 Micro SD Card Interface
      3. 3.5.3 SimpleLink CC3301 Wi-Fi 6 and Bluetooth Low-Energy BoosterPack Interface
      4. 3.5.4 AM6442 UART Interface
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
      1. 4.1.1 Board Interface
        1. 4.1.1.1 Boot Switch Configuration
        2. 4.1.1.2 Starting up the Reference Design
    2. 4.2 Software Requirements
      1. 4.2.1 PoDL PSE Protocol Programming
      2. 4.2.2 Create an SD Card Image With U-Boot and Linux
    3. 4.3 Test Setup and Procedure
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Documentation Support
    3. 5.3 Support Resources
    4. 5.4 Trademarks
  12. 6About the Author

2.3.2 DP83867 gigabit Ethernet Physical Transceiver

The DP83867 device is a robust, low power, fully-featured physical layer transceiver (PHY) with integrated physical medium dependent (PMD) sublayers to support 10BASE-Te, 100BASE-TX, and 1000BASE-T Ethernet protocols. The device is designed for easy implementation of 10-, 100-, 1000-Mbps Ethernet LANs. The device interfaces directly to twisted pair media via an external transformer. This device interfaces directly to the media access controller (MAC) layer through the IEEE 802.3 Standard Media Independent Interface (MII), the IEEE 802.3 Gigabit Media Independent Interface (GMII) or Reduced GMII (RGMII). This reference design used the RGMII interface for the connection between MAC and PHY.