The DS90CF383B transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 227 Mbytes/sec. The DS90CF383B is fixed as a Falling edge strobe transmitter and will interoperate with a Falling edge strobe Receiver (DS90CF386) without any translation logic.
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
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|Part number||Order||Function||Color depth (bpp)||Pixel clock min (MHz)||Pixel clock (Max) (MHz)||Input compatibility||Output compatibility||Features||Signal conditioning||EMI reduction||Diagnostics||Total throughput (Mbps)||Rating||Operating temperature range (C)||Package Group||Package size: mm2:W x L (PKG)|
Supports VGA, SVGA, XGA, and Dual Pixel SXGA
PLL Requires No External Components
Input Clock Detection
No Special Start-up Sequence Required Between Clock/Data and /PD Pins
|1800||Catalog||-10 to 70||TSSOP | 56||56TSSOP: 113 mm2: 8.1 x 14 (TSSOP | 56)|