The LMH0341/0041/0071/0051 SDI Deserializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. When paired with a host FPGA the LMH0341 automatically detects the incoming data rate and decodes the raw 5-bit data words compliant to any of the following standards: DVB-ASI, SMPTE 259M, SMPTE 292M, or SMPTE 424M. See for details on which Standards are supported per device.
The interface between the LMH0341 and the host FPGA consists of a 5-bit wide LVDS bus, an LVDS clock and an SMBus interface. No external VCOs or clocks are required. The LMH0341 CDR detects the frequency from the incoming data stream, generates a clean clock and transmits both clock and data to the host FPGA. The LMH0341, LMH0041 and LMH0071 include a serial reclocked loopthrough with integrated SMPTE compliant cable driver. Refer to for a complete listing of single channel deserializers offered in this family.
The FPGA-Attach SER/DES product family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The product is packaged in a physically small 48 pin WQFN package.
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|Part number||Order||Function||Data rate (Max) (Gbps)||Power consumption (mW)||Control interface||Package Group||Package size: mm2:W x L (PKG)||Operating temperature range (C)|
||Deserializer||2.97||520||Pin/SMBus||WQFN | 48||48WQFN: 49 mm2: 7 x 7 (WQFN | 48)||-40 to 85|
||Deserializer||1.485||705||Pin/I2C||TQFP | 64||64TQFP: 144 mm2: 12 x 12 (TQFP | 64)||0 to 70|
||Deserializer||1.485||480||Pin/SMBus||WQFN | 48||48WQFN: 49 mm2: 7 x 7 (WQFN | 48)||-40 to 85|