LMH0346

ACTIVE

3G HD/SD SDI reclocker with dual differential outputs

Product details

Function Reclocker Supply voltage (V) 3.3 Power consumption (mW) 365 Data rate (max) (Mbps) 2970 Control interface Pin, SMBus Operating temperature range (°C) -40 to 85
Function Reclocker Supply voltage (V) 3.3 Power consumption (mW) 365 Data rate (max) (Mbps) 2970 Control interface Pin, SMBus Operating temperature range (°C) -40 to 85
HTSSOP (PWP) 20 41.6 mm² 6.5 x 6.4 WQFN (NHZ) 24 20 mm² 5 x 4
  • Supports SMPTE 424M, SMPTE 292M, and SMPTE 259M (C) Serial Digital Video Standards
  • Supports 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps Serial Data Rate Operation
  • Supports DVB-ASI at 270 Mbps
  • Single 3.3V Supply Operation
  • 370 mW Typical Power Consumption
  • Two Differential, Reclocked Outputs
  • Choice of Second Reclocked Output or Low-Jitter, Differential, Data-Rate Clock Output
  • Single 27 MHz External Crystal or Reference Clock Input
  • Manual or Automatic Rate Select Input
  • SD/HD Operating Rate Indicator Output
  • Lock Detect Indicator Output
  • Output Mute Function for Data and Clock
  • Auto/Manual Reclocker Bypass
  • Differential LVPECL Compatible Serial Data Inputs and Outputs
  • LVCMOS Control Inputs and Indicator Outputs
  • 20-Pin HTSSOP or 24-Pin WQFN Package
  • Industrial Temperature Range: -40°C to +85°C
  • Footprint Compatible With the LMH0046 and LMH0026 (HTSSOP Package)

All trademarks are the property of their respective owners.

  • Supports SMPTE 424M, SMPTE 292M, and SMPTE 259M (C) Serial Digital Video Standards
  • Supports 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps Serial Data Rate Operation
  • Supports DVB-ASI at 270 Mbps
  • Single 3.3V Supply Operation
  • 370 mW Typical Power Consumption
  • Two Differential, Reclocked Outputs
  • Choice of Second Reclocked Output or Low-Jitter, Differential, Data-Rate Clock Output
  • Single 27 MHz External Crystal or Reference Clock Input
  • Manual or Automatic Rate Select Input
  • SD/HD Operating Rate Indicator Output
  • Lock Detect Indicator Output
  • Output Mute Function for Data and Clock
  • Auto/Manual Reclocker Bypass
  • Differential LVPECL Compatible Serial Data Inputs and Outputs
  • LVCMOS Control Inputs and Indicator Outputs
  • 20-Pin HTSSOP or 24-Pin WQFN Package
  • Industrial Temperature Range: -40°C to +85°C
  • Footprint Compatible With the LMH0046 and LMH0026 (HTSSOP Package)

All trademarks are the property of their respective owners.

The LMH0346 3 Gbps HD/SD SDI Reclocker retimes serial digital video data conforming to the SMPTE 424M, SMPTE 292M, and SMPTE 259M (C) standards. The LMH0346 operates at serial data rates of 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps. The LMH0346 supports DVB-ASI operation at 270 Mbps.

The LMH0346 automatically detects the incoming data rate and adjusts itself to retime the incoming data to suppress accumulated jitter. The LMH0346 recovers the serial data-rate clock and optionally provides it as an output. The LMH0346 has two differential serial data outputs; the second output may be selected as a low-jitter, data-rate clock output. Controls and indicators are: serial clock or second serial data output select, manual rate select input, SD/HD rate indicator output, lock detect output, auto/manual data bypass and output mute. The serial data inputs, outputs, and serial clock outputs are differential LVPECL compatible. The CML serial data and serial clock outputs are suitable for driving 100Ω differentially terminated networks. The control logic inputs and outputs are LVCMOS compatible.

The LMH0346 is powered from a single 3.3V supply. Power dissipation is typically 370 mW.

The device is available in two space-saving packages: a 6.5 X 4.4 mm 20-pin HTSSOP and an even more space–efficient 5 X 4 mm 24-pin WQFN package.

The LMH0346 3 Gbps HD/SD SDI Reclocker retimes serial digital video data conforming to the SMPTE 424M, SMPTE 292M, and SMPTE 259M (C) standards. The LMH0346 operates at serial data rates of 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps. The LMH0346 supports DVB-ASI operation at 270 Mbps.

The LMH0346 automatically detects the incoming data rate and adjusts itself to retime the incoming data to suppress accumulated jitter. The LMH0346 recovers the serial data-rate clock and optionally provides it as an output. The LMH0346 has two differential serial data outputs; the second output may be selected as a low-jitter, data-rate clock output. Controls and indicators are: serial clock or second serial data output select, manual rate select input, SD/HD rate indicator output, lock detect output, auto/manual data bypass and output mute. The serial data inputs, outputs, and serial clock outputs are differential LVPECL compatible. The CML serial data and serial clock outputs are suitable for driving 100Ω differentially terminated networks. The control logic inputs and outputs are LVCMOS compatible.

The LMH0346 is powered from a single 3.3V supply. Power dissipation is typically 370 mW.

The device is available in two space-saving packages: a 6.5 X 4.4 mm 20-pin HTSSOP and an even more space–efficient 5 X 4 mm 24-pin WQFN package.

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Technical documentation

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Type Title Date
* Data sheet LMH0346 3 Gbps HD/SD SDI Reclocker with Dual Differential Outputs datasheet (Rev. J) 15 Apr 2013
Selection guide Broadcast and Professional Video Interface Solutions (Rev. E) 05 Apr 2017
Application note AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) 26 Apr 2013
Application note AN-1977 LMH0346 Customization with SMBus (Rev. A) 26 Apr 2013
Application note AN-2004 Replacing the CLC016 Reclocker with the LMH0026 (Rev. A) 26 Apr 2013
Application note AN-2145 Power Considerations for SDI Products (Rev. B) 26 Apr 2013
Application note AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) 26 Apr 2013
User guide SD3GDAEVK User Guide 05 Apr 2013
User guide 3 Gbps HD SD SDI Reclocker with Dual Differential Outputs Eval Bd User Guide 26 Jan 2012
Application note High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems 12 Nov 2009
Application note Reference Clock Loop Through Application 16 Jan 2009
Design guide Broadcast Video Owner's Manual 17 Nov 2006

Design & development

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Package Pins CAD symbols, footprints & 3D models
HTSSOP (PWP) 20 Ultra Librarian
WQFN (NHZ) 24 Ultra Librarian

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