SN65DSI83 Single-channel MIPI® DSI to single-link LVDS bridge & FlatLink™ integrated circuit | TI.com

SN65DSI83
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Single-channel MIPI® DSI to single-link LVDS bridge & FlatLink™ integrated circuit

 

Recommended alternative parts

  • SN65DSI83-Q1  -  Automotive grade with temperature range from –40°C to +125°C

Description

The SN65DSI83 DSI to FlatLink bridge device features a single-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18 bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink-compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Single-Link LVDS with four data lanes per link.

The SN65DSI83 device can support up to WUXGA 1920 × 1200 at 60 frames per second, at 24 bpp with reduced blanking. The SN65DSI83 device is also suitable for applications using 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.

Designed with industry-compliant interface technology, the SN65DSI83 device is compatible with a wide range of microprocessors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI defined ultra-low power state (ULPS) support.

The SN65DSI83 device is implemented in a small outline 5-mm × 5-mm BGA MICROSTAR JUNIOR at 0.5-mm pitch package, and operates across a temperature range from –40ºC to 85ºC.

Features

  • Implements MIPI® D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
  • Single Channel DSI Receiver Configurable for 1, 2, 3, or 4 D-PHY Data Lanes Per Channel Operating up to 1 Gbps/Lane
  • Supports 18 bpp and 24 bpp DSI Video Packets With RGB666 and RGB888 Formats
  • Max Resolution up to 60 fps WUXGA
    1920 × 1200 at 18 bpp and 24 bpp Color With Reduced Blanking. Suitable for 60 fps 1366 × 768 / 1280 × 800 at 18 bpp and 24 bpp
  • FlatLink™ Output for Single-Link LVDS
  • Supports Single Channel DSI to Single-Link LVDS Operating Mode
  • LVDS Output Clock Range of 25 MHz to 154 MHz
  • LVDS Pixel Clock May be Sourced from Free-Running Continuous D-PHY Clock or External Reference Clock (REFCLK)
  • 1.8-V Main VCC Power Supply
  • Low Power Features Include Shutdown Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI Ultra-Low Power State (ULPS) Support
  • LVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB Routing
  • ESD Rating ±2 kV (HBM)
  • Packaged in 64-pin 5-mm × 5-mm BGA MICROSTAR JUNIOR (ZQE)
  • Temperature Range: –40°C to 85°C

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Parametrics

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Part number Order Protocols Speed (Max) (Gbps) Package Group Package size: mm2:W x L (PKG) Operating temperature range (C)
SN65DSI83 Order now     BGA MICROSTAR JUNIOR | 64     64BGA MICROSTAR JUNIOR: 25 mm2: 5 x 5 (BGA MICROSTAR JUNIOR | 64)     -40 to 85    
SN65DSI84 Samples not available     BGA MICROSTAR JUNIOR | 64     64BGA MICROSTAR JUNIOR: 25 mm2: 5 x 5 (BGA MICROSTAR JUNIOR | 64)     -40 to 85    
SN65DSI85 Samples not available DisplayPort     8     BGA MICROSTAR JUNIOR | 64     64BGA MICROSTAR JUNIOR: 25 mm2: 5 x 5 (BGA MICROSTAR JUNIOR | 64)     -40 to 85