SN74ACT74 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset | TI.com

SN74ACT74
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Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset

Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset - SN74ACT74
Datasheet
 

Description

The ’ACT74 dual positive-edge-triggered devices are D-type flip-flops.

A low level at the preset (PRE)\ or clear (CLR)\ input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.

Features

  • 4.5-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 10.5 ns at 5 V
  • Inputs Are TTL-Voltage Compatible

Parametrics

Compare all products in D-type flip-flop Email Download to Excel
Part number Order Technology Family Input type Output type VCC (Min) (V) VCC (Max) (V) IOL (Max) (mA) IOH (Max) (mA) Rating Package Group
SN74ACT74 Order now ACT     TTL     CMOS     4.5     5.5     24     -24     Catalog     PDIP | 14
SOIC | 14
SO | 14
SSOP | 14
TSSOP | 14    
SN54ACT74 Samples not available ACT     TTL     CMOS     4.5     5.5     24     -24     Military     CDIP | 14
CFP | 14
LCCC | 20