SN75LVDS86

ACTIVE

FlatLink™ Receiver

Product details

Protocols Catalog Rating Catalog Operating temperature range (°C) 0 to 70
Protocols Catalog Rating Catalog Operating temperature range (°C) 0 to 70
TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • 3:21 Data Channel Expansion at up to 178.5 Mbytes/s Throughput
  • Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI
  • Three Data Channels and Clock Low-Voltage Differential Channels In and 21 Data and Clock Low-Voltage TTL Channels Out
  • Operates From a Single 3.3-V Supply and 250 mW (Typ)
  • 5-V Tolerant SHTDN Input
  • ESD Protection Exceeds 4 kV on Bus Pins
  • Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch
  • Consumes Less Than 1 mW When Disabled
  • Wide Phase-Lock Input Frequency Range 31 MHz to 68 MHz
  • No External Components Required for PLL
  • Open-Circuit Receiver Fail-Safe Design
  • Inputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
  • Improved Replacement for the National™ DS90C562

FlatLink is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

  • 3:21 Data Channel Expansion at up to 178.5 Mbytes/s Throughput
  • Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI
  • Three Data Channels and Clock Low-Voltage Differential Channels In and 21 Data and Clock Low-Voltage TTL Channels Out
  • Operates From a Single 3.3-V Supply and 250 mW (Typ)
  • 5-V Tolerant SHTDN Input
  • ESD Protection Exceeds 4 kV on Bus Pins
  • Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch
  • Consumes Less Than 1 mW When Disabled
  • Wide Phase-Lock Input Frequency Range 31 MHz to 68 MHz
  • No External Components Required for PLL
  • Open-Circuit Receiver Fail-Safe Design
  • Inputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
  • Improved Replacement for the National™ DS90C562

FlatLink is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

The SN75LVDS86 FlatLink receiver contains three serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, '83, '84, or '85, over four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage TTL (LVTTL) synchronous data at a lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN75LVDS86 presents valid data on the falling edge of the output clock (CLKOUT).

The SN75LVDS86 requires only four line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level.

The LVDS receivers of the SN75LVDS86 include an open-circuit fail-safe design such that when the inputs are not connected to an LVDS driver, the receiver outputs go to a low-level. This occurs even when the line is differentially terminated at the receiver inputs.

The SN75LVDS86 is characterized for operation over ambient free-air temperatures of 0°C to 70°C.

The SN75LVDS86 FlatLink receiver contains three serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, '83, '84, or '85, over four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage TTL (LVTTL) synchronous data at a lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN75LVDS86 presents valid data on the falling edge of the output clock (CLKOUT).

The SN75LVDS86 requires only four line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level.

The LVDS receivers of the SN75LVDS86 include an open-circuit fail-safe design such that when the inputs are not connected to an LVDS driver, the receiver outputs go to a low-level. This occurs even when the line is differentially terminated at the receiver inputs.

The SN75LVDS86 is characterized for operation over ambient free-air temperatures of 0°C to 70°C.

Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 4
Type Title Date
* Data sheet Flatlink Receiver datasheet (Rev. D) 10 May 2006
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 09 Nov 2018
Application note Flatlink Data Transmission System Design Overview (Rev. A) 01 Jun 2001
Application note Time Budgeting of the Flatlink Interface Application Report 11 Jun 1997

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

SN75LVDS86 IBIS Model

SLLC109.ZIP (6 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Package Pins CAD symbols, footprints & 3D models
TSSOP (DGG) 48 Ultra Librarian

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos