Support software
200-MHz, LVCMOS, custom-programmed 3-PLL clock synthesizer, multiplier & divider
Data sheet
Although this product continues to be in production to support previous designs, we don't recommend it for new designs. Consider one of these alternates:
CDC706
Technical documentation
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View all 4 Type | Title | Date | ||
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* | Data sheet | Programmable 3-PLL Clock Synthesizer / Multiplier / Divider datasheet (Rev. B) | 11 Feb 2008 | |
Application note | High Speed Layout Guidelines (Rev. A) | 08 Aug 2017 | ||
Application note | CDCx706/x906 Termination and Signal Integrity Guidelines (Rev. A) | 28 Nov 2007 | ||
Application note | Clock Recommendations for the DM643x EVM | 29 Nov 2006 |
Design & development
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Simulation tool
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Package | Pins | Download |
---|---|---|
TSSOP (PW) | 20 | View options |
Ordering & quality
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