The DS90CR485 device serializes the 24 LVCMOS/LVTTL double-edge inputs (48 bits data latched in per clock cycle) onto eight Low Voltage Differential Signaling (LVDS) streams. A phase-locked transmit clock is also in parallel with the data streams over a 9th LVDS link. The reduction of the wide TTL bus to a few LVDS lines reduces cable and connector size and cost. The double-edge input strobes data on both the rising and falling edges of the clock. This minimizes the pin count required and simplifies PCB routing between the host chip and the serializer.
This chip can help resolve EMI and interconnect size problems for high throughput point-to-point applications.
The DS90CR485 is compatible with the DS90CR486 Channel-Link receiver. The device is also backward-compatible with other Channel-Link receivers such as the DS90CR482 and DS90CR484.
| Typ | Titel | Datum | ||
|---|---|---|---|---|
| * | Data sheet | DS90CR485 133-MHz, 48-Bit Channel Link Serializer (6.384 Gbps) datasheet (Rev. E) | 10 Sep 2019 | |
| Application note | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 09 Nov 2018 | ||
| EVM User's guide | 48-bit Channel Link Serializer Deserializer Evaluation Board 133MHz | 26 Jan 2012 | ||
| Design guide | Channel Link I Design Guide | 29 Mär 2007 | ||
| Application note | Multi-Drop Channel-Link Operation | 04 Okt 2004 | ||
| White paper | The Many Flavors of LVDS | 01 Feb 2002 | ||
| Application note | CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications | 05 Okt 1998 |
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| Gehäuse | Pins | Herunterladen |
|---|---|---|
| QFP (NEZ) | 100 | Optionen anzeigen |
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