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SN54HC590A

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Binärzähler, 8 Bit, mit Tri-State-Ausgangsregistern

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Datenblatt

SN54HC590A

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Produktdetails

Function Counter Bits (#) 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type 3-State Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Function Counter Bits (#) 8 Technology family HC Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Input type Standard CMOS Output type 3-State Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm² 19.56 x 6.92 CFP (W) 16 69.319 mm² 10.3 x 6.73 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • 2-V to 6-V VCC Operation
  • High-Current 3-State Parallel Register Outputs Can Drive Up to 15 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 14 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • 8-Bit Counter With Register
  • Counter Has Direct Clear
  • 2-V to 6-V VCC Operation
  • High-Current 3-State Parallel Register Outputs Can Drive Up to 15 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 14 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • 8-Bit Counter With Register
  • Counter Has Direct Clear

The 'HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features direct clear (CCLR)\ and count-enable (CCKEN)\ inputs. A ripple-carry output (RCO)\ is provided for cascading. Expansion is accomplished easily for two stages by connecting RCO\ of the first stage to CCKEN\ of the second stage. Cascading for larger count chains can be accomplished by connecting RCO\ of each stage to the counter clock (CCLK) input of the following stage.

CCLK and the register clock (RCLK) inputs are positive-edge triggered. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable.

The 'HC590A devices contain an 8-bit binary counter that feeds an 8-bit storage register. The storage register has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The binary counter features direct clear (CCLR)\ and count-enable (CCKEN)\ inputs. A ripple-carry output (RCO)\ is provided for cascading. Expansion is accomplished easily for two stages by connecting RCO\ of the first stage to CCKEN\ of the second stage. Cascading for larger count chains can be accomplished by connecting RCO\ of each stage to the counter clock (CCLK) input of the following stage.

CCLK and the register clock (RCLK) inputs are positive-edge triggered. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable.
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Technische Dokumentation

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Alle anzeigen 15
Typ Titel Datum
* Data sheet SN54HC590A, SN74HC590A datasheet (Rev. F) 15 Sep 2003
* SMD SN54HC590A SMD 5962-89603 21 Jun 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Okt 1996
Application note Live Insertion 01 Okt 1996
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 Mai 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design und Entwicklung

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Gehäuse Pins Herunterladen
CDIP (J) 16 Optionen anzeigen
CFP (W) 16 Optionen anzeigen
LCCC (FK) 20 Optionen anzeigen
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  • REACH
  • Bausteinkennzeichnung
  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
  • MTBF-/FIT-Schätzungen
  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
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