Startseite Schnittstelle LVDS-, M-LVDS- und PECL-ICs

SN65LVDS100

AKTIV

Puffer, Repeater & Umsetzer, LVDS, LVPECL & CML zu LVDS, 2 Gbit/s

Produktdetails

Function Repeater, Translator Protocols CML, LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 2000 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Repeater, Translator Protocols CML, LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 2000 Input signal CML, LVDS, LVPECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² 4.9 x 6 VSSOP (DGK) 8 14.7 mm² 3 x 4.9
  • Designed for Signaling Rates ≥ 2 Gbps
  • Total Jitter < 65 ps
  • Low-Power Alternative for the MC100EP16
  • Low 100-ps (Maximum) Part-to-Part Skew
  • 25 mV of Receiver Input Threshold Hysteresis
    Over 0-V to 4-V Input Voltage Range
  • Inputs Electrically Compatible With LVPECL,
    CML, and LVDS Signal Levels
  • 3.3-V Supply Operation
  • LVDT Integrates 110-Ω Terminating Resistor
  • Offered in SOIC and MSOP
  • Designed for Signaling Rates ≥ 2 Gbps
  • Total Jitter < 65 ps
  • Low-Power Alternative for the MC100EP16
  • Low 100-ps (Maximum) Part-to-Part Skew
  • 25 mV of Receiver Input Threshold Hysteresis
    Over 0-V to 4-V Input Voltage Range
  • Inputs Electrically Compatible With LVPECL,
    CML, and LVDS Signal Levels
  • 3.3-V Supply Operation
  • LVDT Integrates 110-Ω Terminating Resistor
  • Offered in SOIC and MSOP

The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 are high-speed differential receivers and drivers connected as repeaters. The receiver accepts low-voltage differential signaling (LVDS), positive-emitter-coupled logic (PECL), or current-mode logic (CML) input signals at rates up to 2 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.

The outputs of the SN65LVDS100 and SN65LVDT100 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDS101 and SN65LVDT101 are compatible with 3.3-V PECL levels. Both drive differential transmission lines with nominally 100-Ω characteristic impedance.

The SN65LVDT100 and SN65LVDT101 include a 110-Ω differential line termination resistor for less board space, fewer components, and the shortest stub length possible. They do not include the VBB voltage reference found in the SN65LVDS100 and SN65LVDS101. VBB provides a voltage reference of typically 1.35 V below VCC for use in receiving single-ended input signals and is particularly useful with single-ended 3.3-V PECL inputs. When VBB is not used, it should be unconnected or open.

All devices are characterized for operation from –40°C to 85°C.

The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 are high-speed differential receivers and drivers connected as repeaters. The receiver accepts low-voltage differential signaling (LVDS), positive-emitter-coupled logic (PECL), or current-mode logic (CML) input signals at rates up to 2 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.

The outputs of the SN65LVDS100 and SN65LVDT100 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDS101 and SN65LVDT101 are compatible with 3.3-V PECL levels. Both drive differential transmission lines with nominally 100-Ω characteristic impedance.

The SN65LVDT100 and SN65LVDT101 include a 110-Ω differential line termination resistor for less board space, fewer components, and the shortest stub length possible. They do not include the VBB voltage reference found in the SN65LVDS100 and SN65LVDS101. VBB provides a voltage reference of typically 1.35 V below VCC for use in receiving single-ended input signals and is particularly useful with single-ended 3.3-V PECL inputs. When VBB is not used, it should be unconnected or open.

All devices are characterized for operation from –40°C to 85°C.

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Technische Dokumentation

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Typ Titel Datum
* Data sheet SN65LVDx10x Differential Translator/Repeater datasheet (Rev. E) PDF | HTML 20 Jul 2015
Application brief How to Use a 3.3-V LVDS Buffer as a Low-Voltage LVDS Driver 09 Jan 2019
Application note Signaling Rate vs. Distance for Differential Buffers 26 Jan 2010
Application note AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) 17 Okt 2007
Application note DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML 19 Feb 2003
EVM User's guide 2-GBPS Differential Repeater EVM (Rev. A) 11 Nov 2002
More literature HPL EVM Program 29 Aug 2002
EVM User's guide 2-GBPS Differential Repeater EVM 08 Aug 2002

Design und Entwicklung

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Evaluierungsplatine

SN65CML100EVM — SN65CML100-Evaluierungsmodul

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Benutzerhandbuch: PDF
Evaluierungsplatine

SN65LVDS100EVM — SN65LVDS100-Evaluierungsmodul

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Benutzerhandbuch: PDF
Simulationsmodell

SN65LVDS100 IBIS Model

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Simulationstool

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Simulationstool

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TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Benutzerhandbuch: PDF
Referenzdesigns

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Referenzdesigns

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Design guide: PDF
Schaltplan: PDF
Gehäuse Pins Herunterladen
SOIC (D) 8 Optionen anzeigen
VSSOP (DGK) 8 Optionen anzeigen

Bestellen & Qualität

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  • Materialinhalt
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