The 'ALS193A are synchronous, reversible, 4-bit up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters.
The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count/clock (UP or DOWN) input. The direction of the count is determined by which count input is pulsed while the other count input is high.
All four counters are fully programmable; that is, each output may
be preset to either level by placing a low on the load (
) input and entering the desired
data at the data inputs. The output changes to agree with the data
inputs independently of the count pulses. This feature allows the
counters to be used as modulo-N dividers by simply modifying the
count length with the preset inputs.
A high level applied to the clear (CLR) input forces all outputs
to the low level. The clear function is independent of the count and
i nputs. The
UP, DOWN, and inputs are
buffered to lower the drive requirement, which significantly reduces
the loading on, or current required by, clock drivers, etc., for long
parallel words.
These counters are designed to be cascaded without the need for
external circuitry. The borrow (
) output produces a low-level pulse while the count is
zero (all Q outputs low) and the DOWN input is low. Similarily, the
carry (CO\) output produces a low-level pulse while the count is 9 or
15 (all Q outputs high) and the UP input is low. The counters can
then be easily cascaded by feeding and 
to the
count-down and count-up inputs, respectively, of the succeeding
counter.
The SN54ALS193A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS193A is characterized for operation from 0°C to 70°C.
| Typ | Titel | Datum | ||
|---|---|---|---|---|
| * | Data sheet | Synchronous 4-Bit Up/Down Binary Counters With Dual Clock And Clear datasheet (Rev. C) | 01 Jul 1996 | |
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dez 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 01 Aug 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 Okt 1996 | ||
| Application note | Live Insertion | 01 Okt 1996 | ||
| Application note | Advanced Schottky (ALS and AS) Logic Families | 01 Aug 1995 |
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Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.
| Gehäuse | Pins | Herunterladen |
|---|---|---|
| PDIP (N) | 16 | Optionen anzeigen |
| SOIC (D) | 16 | Optionen anzeigen |
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