SN74LVC1G139

Name: SN74LVC1G139
Brand: TI
SKU: SN74LVC1G139
Price: 0.355 USD

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Decoder, 2 Leitungen auf 4 Leitungen

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Datenblatt

document-pdfAcrobat SN74LVC1G139 2-to-4 Line Decoder datasheet (Rev. E) (Englisch) PDF | HTML

SN74LVC1G139

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Datenblatt

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Produktdetails

Technology family

LVC

Number of channels

1

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Supply current (max) (µA)

10

Technology family

LVC

Number of channels

1

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Supply current (max) (µA)

10

DSBGA (YZP)

8

2.8125 mm² 2.25 x 1.25

SSOP (DCT)

8

11.8 mm² 2.95 x 4

VSSOP (DCU)

8

6.2 mm² 2 x 3.1

Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to V_CC
Maximum t_pd of 4.9 ns at 3.3 V and 15 pF
Low Power Consumption, 10-µA Maximum I_CC
±24-mA Output Drive at 3.3 V
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to V_CC
Maximum t_pd of 4.9 ns at 3.3 V and 15 pF
Low Power Consumption, 10-µA Maximum I_CC
±24-mA Output Drive at 3.3 V
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This SN74LVC1G139 2-to-4 line decoder is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC1G139 2-line to 4-line decoder is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When used with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

NanoStar and NanoFree package technology is a major breakthrough in device packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This SN74LVC1G139 2-to-4 line decoder is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC1G139 2-line to 4-line decoder is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When used with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

NanoStar and NanoFree package technology is a major breakthrough in device packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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	Typ	Titel		Datum
*	Data sheet	SN74LVC1G139 2-to-4 Line Decoder datasheet (Rev. E)	PDF \| HTML	09 Jan 2018
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		26 Jul 2021
	Selection guide	Little Logic Guide 2018 (Rev. G)		06 Jul 2018
	Selection guide	Logic Guide (Rev. AB)		12 Jun 2017
	Application note	How to Select Little Logic (Rev. A)		26 Jul 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		02 Dez 2015
	User guide	LOGIC Pocket Data Book (Rev. B)		16 Jan 2007
	Product overview	Design Summary for WCSP Little Logic (Rev. B)		04 Nov 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)		22 Jun 2004
	User guide	Signal Switch Data Book (Rev. A)		14 Nov 2003
	Application note	Use of the CMOS Unbuffered Inverter in Oscillator Circuits		06 Nov 2003
	User guide	LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)		18 Dez 2002
	Application note	Texas Instruments Little Logic Application Report		01 Nov 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		29 Aug 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards		13 Jun 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)		22 Mai 2002
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices		10 Mai 2002
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS		27 Mär 2002
	Application note	Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices		01 Dez 1997
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)		01 Aug 1997
	Application note	CMOS Power Consumption and CPD Calculation (Rev. B)		01 Jun 1997
	Application note	LVC Characterization Information		01 Dez 1996
	Application note	Input and Output Characteristics of Digital Integrated Circuits		01 Okt 1996
	Application note	Live Insertion		01 Okt 1996
	Design guide	Low-Voltage Logic (LVC) Designer's Guide		01 Sep 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide		01 Mai 1996

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Evaluierungsplatine

5-8-LOGIC-EVM — Generisches Logik-Evaluierungsmodul für 5- bis 8-polige DCK-, DCT-, DCU-, DRL- und DBV-Gehäuse

Flexibles EVM zur Unterstützung aller Geräte mit 5- bis 8-poligem DCK-, DCT-, DCU-, DRL- oder DBV-Gehäuse.

Benutzerhandbuch: PDF

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Simulationsmodell

SN74LVC1G139 IBIS Model (Rev. A)

SCEM449A.ZIP (44 KB) - IBIS Model

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Referenzdesigns

TIDA-01565 — Referenzdesign für drahtgebundene ODER MUX- und PGA-Lösungen

This board demonstrates a wired-OR multiplexer (MUX) and a programmable gain amplifier (PGA) application of the OPA837 operational amplifier. These applications are made possible with the high-impedance output of the amplifier and the high-impedance inverting input while in power-down (PD) mode. It (...)

Design guide: PDF

Schaltplan: PDF

Gehäuse	Pins	Herunterladen
DSBGA (YZP)	8	Optionen anzeigen
SSOP (DCT)	8	Optionen anzeigen
VSSOP (DCU)	8	Optionen anzeigen

Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

SN74LVC1G139

Decoder, 2 Leitungen auf 4 Leitungen

SN74LVC1G139

Produktdetails

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