TLV571

AKTIV

8 Bit, 1,25 MSPS, ein Kanal, Hardware-Konfiguration, energieeffizient, mit Auto oder SW-Abschaltung

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Datenblatt

document-pdfAcrobat 2.7 V To 5.5 V, 1-Channel, 8-Bit Parallel ADC datasheet (Rev. A) (Englisch)

TLV571

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Resolution (Bits)

8

Sample rate (max) (ksps)

1250

Number of input channels

1

Interface type

Parallel

Architecture

SAR

Input type

Single-ended

Rating

Catalog

Reference mode

External

Input voltage range (max) (V)

5.5

Input voltage range (min) (V)

0

Features

Oscillator

Operating temperature range (°C)

-40 to 85

Power consumption (typ) (mW)

12

Analog supply (min) (V)

2.7

Analog supply voltage (max) (V)

5.5

SNR (dB)

49

Digital supply (min) (V)

2.7

Digital supply (max) (V)

5.5

Resolution (Bits)

8

Sample rate (max) (ksps)

1250

Number of input channels

1

Interface type

Parallel

Architecture

SAR

Input type

Single-ended

Rating

Catalog

Reference mode

External

Input voltage range (max) (V)

5.5

Input voltage range (min) (V)

0

Features

Oscillator

Operating temperature range (°C)

-40 to 85

Power consumption (typ) (mW)

12

Analog supply (min) (V)

2.7

Analog supply voltage (max) (V)

5.5

SNR (dB)

49

Digital supply (min) (V)

2.7

Digital supply (max) (V)

5.5

SOIC (DW)

24

159.65 mm² 15.5 x 10.3

TSSOP (PW)

24

49.92 mm² 7.8 x 6.4

Fast Throughput Rate: 1.25 MSPS at 5 V, 625 KSPS at 3 V
Wide Analog Input: 0 V to AV_DD
Differential Nonlinearity Error: < ± 0.5 LSB
Integral Nonlinearity Error: < ± 0.5 LSB
Single 2.7-V to 5.5-V Supply Operation
Low Power: 12 mW at 3 V and 35 mW at 5 V
Auto Power Down of 1 mA Max
Software Power Down: 10 uA Max
Internal OSC
Hardware Configurable
DSP and Microcontroller Compatible Parallel Interface
Binary/Twos Complement Output
Hardware Controlled Extended Sampling
Hardware or Software Start of Conversion
Applications
- Mass Storage and HDD
- Automotive
- Digital Servos
- Process Control
- General-Purpose DSP
- Image Sensor Processing

Fast Throughput Rate: 1.25 MSPS at 5 V, 625 KSPS at 3 V
Wide Analog Input: 0 V to AV_DD
Differential Nonlinearity Error: < ± 0.5 LSB
Integral Nonlinearity Error: < ± 0.5 LSB
Single 2.7-V to 5.5-V Supply Operation
Low Power: 12 mW at 3 V and 35 mW at 5 V
Auto Power Down of 1 mA Max
Software Power Down: 10 uA Max
Internal OSC
Hardware Configurable
DSP and Microcontroller Compatible Parallel Interface
Binary/Twos Complement Output
Hardware Controlled Extended Sampling
Hardware or Software Start of Conversion
Applications
- Mass Storage and HDD
- Automotive
- Digital Servos
- Process Control
- General-Purpose DSP
- Image Sensor Processing

The TLV571 is an 8-bit data acquisition system that combines a high-speed 8-bit ADC and a parallel interface. The device contains two on-chip control registers allowing control of software conversion start and power down via the bidirectional parallel port. The control registers can be set to a default mode using a dummy RD\ while WR\ is tied low allowing the registers to be hardware configurable.

The TLV571 operates from a single 2.7-V to 5.5-V power supply. It accepts an analog input range from 0 V to AV_DD and digitizes the input at a maximum 1.25 MSPS throughput rate at 5 V. The power dissipations are only 12 mW with a 3-V supply or 35 mW with a 5-V supply. The device features an auto power-down mode that automatically powers down to 1 mA 50 ns after conversion is performed. In software power-down mode, the ADC is further powered down to only 10 uA.

Very high throughput rate, simple parallel interface, and low power consumption make the TLV571 an ideal choice for high-speed digital signal processing.

The TLV571 is an 8-bit data acquisition system that combines a high-speed 8-bit ADC and a parallel interface. The device contains two on-chip control registers allowing control of software conversion start and power down via the bidirectional parallel port. The control registers can be set to a default mode using a dummy RD\ while WR\ is tied low allowing the registers to be hardware configurable.

The TLV571 operates from a single 2.7-V to 5.5-V power supply. It accepts an analog input range from 0 V to AV_DD and digitizes the input at a maximum 1.25 MSPS throughput rate at 5 V. The power dissipations are only 12 mW with a 3-V supply or 35 mW with a 5-V supply. The device features an auto power-down mode that automatically powers down to 1 mA 50 ns after conversion is performed. In software power-down mode, the ADC is further powered down to only 10 uA.

Very high throughput rate, simple parallel interface, and low power consumption make the TLV571 an ideal choice for high-speed digital signal processing.

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Alle anzeigen 4

	Typ	Titel	Datum
*	Data sheet	2.7 V To 5.5 V, 1-Channel, 8-Bit Parallel ADC datasheet (Rev. A)	09 Feb 2000
	E-book	Best of Baker's Best: Precision Data Converters -- SAR ADCs	21 Mai 2015
	Application note	Determining Minimum Acquisition Times for SAR ADCs, part 2	17 Mär 2011
	User guide	Characteristics, Operation, and Use of the TLV571/TLV157x EVM (Rev. A)	30 Nov 2000

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SOIC (DW)	24	Optionen anzeigen
TSSOP (PW)	24	Optionen anzeigen

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TLV571

8 Bit, 1,25 MSPS, ein Kanal, Hardware-Konfiguration, energieeffizient, mit Auto oder SW-Abschaltung

TLV571

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