DS90LV001

ACTIVE

800-Mbps LVDS buffer

Product details

Function Buffer Protocols LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 800 Input signal LVCMOS, LVDS, LVPECL, LVTTL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Buffer Protocols LVDS, LVPECL Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 800 Input signal LVCMOS, LVDS, LVPECL, LVTTL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² 4.9 x 6 WSON (NGK) 8 9 mm² 3 x 3
  • Single +3.3 V Supply
  • LVDS Receiver Inputs Accept LVPECL Signals
  • TRI-STATE Outputs
  • Receiver Input Threshold < ±100 mV
  • Fast Propagation Delay of 1.4 ns (Typ)
  • Low Jitter 800 Mbps Fully Differential Data Path
  • 100 ps (Typ) of pk-pk Jitter with PRBS = 223−1 Data Pattern at 800 Mbps
  • Compatible with ANSI/TIA/EIA-644-A LVDS Standard
  • 8 pin SOIC and Space Saving (70%) WSON Package
  • Industrial Temperature Range

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  • Single +3.3 V Supply
  • LVDS Receiver Inputs Accept LVPECL Signals
  • TRI-STATE Outputs
  • Receiver Input Threshold < ±100 mV
  • Fast Propagation Delay of 1.4 ns (Typ)
  • Low Jitter 800 Mbps Fully Differential Data Path
  • 100 ps (Typ) of pk-pk Jitter with PRBS = 223−1 Data Pattern at 800 Mbps
  • Compatible with ANSI/TIA/EIA-644-A LVDS Standard
  • 8 pin SOIC and Space Saving (70%) WSON Package
  • Industrial Temperature Range

All trademarks are the property of their respective owners.

The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the designer would like.

The DS90LV001, available in the WSON package, will allow the receiver to be placed very close to the main transmission line, thus improving system performance.

A wide input dynamic range will allow the DS90LV001 to receive differential signals from LVPECL as well as LVDS sources. This will allow the device to also fill the role of an LVPECL-LVDS translator.

An output enable pin is provided, which allows the user to place the LVDS output in TRI-STATE.

The DS90LV001 is offered in two package options, an 8 pin WSON and SOIC.

The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the "stub length" or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the designer would like.

The DS90LV001, available in the WSON package, will allow the receiver to be placed very close to the main transmission line, thus improving system performance.

A wide input dynamic range will allow the DS90LV001 to receive differential signals from LVPECL as well as LVDS sources. This will allow the device to also fill the role of an LVPECL-LVDS translator.

An output enable pin is provided, which allows the user to place the LVDS output in TRI-STATE.

The DS90LV001 is offered in two package options, an 8 pin WSON and SOIC.

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Technical documentation

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Type Title Date
* Data sheet DS90LV001 800 Mbps LVDS Buffer datasheet (Rev. E) 22 Apr 2013
Application brief How to Use a 3.3-V LVDS Buffer as a Low-Voltage LVDS Driver 09 Jan 2019
EVM User's guide 3.3V LVDS-LVDS Buffer Evaluation Board User Guide 27 Jan 2012
Application note Signaling Rate vs. Distance for Differential Buffers 26 Jan 2010
White paper Making the Most of Your LVDS - 5 Tips for Buffering Signal Integrity Headaches 01 Aug 2001
Application note An Overview of LVDS Technology 05 Oct 1998

Design & development

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Simulation model

DS90LV001 IBIS Model

SNLM045.ZIP (29 KB) - IBIS Model
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Package Pins CAD symbols, footprints & 3D models
SOIC (D) 8 Ultra Librarian
WSON (NGK) 8 Ultra Librarian

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