DS90LV110T

ACTIVE

1 to 10 LVDS data/clock distributor

Product details

Function Repeater, Translator Protocols CML, LVDS, PECL Number of transmitters 10 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 800 Input signal LVDS, LVPECL, PECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Repeater, Translator Protocols CML, LVDS, PECL Number of transmitters 10 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (Mbps) 800 Input signal LVDS, LVPECL, PECL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (PW) 28 62.08 mm² 9.7 x 6.4
  • Low jitter 800 Mbps fully differential data path
  • 145 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern at 800 Mbps
  • Single +3.3 V Supply
  • Less than 413 mW (typ) total power dissipation
  • Balanced output impedance
  • Output channel-to-channel skew is 35ps (typ)
  • Differential output voltage (VOD) is 320mV (typ) with 100Ω termination load.
  • LVDS receiver inputs accept LVPECL signals
  • Fast propagation delay of 2.8 ns (typ)
  • Receiver input threshold < ±100 mV
  • 28 lead TSSOP package
  • Conforms to ANSI/TIA/EIA-644 LVDS standard

All trademarks are the property of their respective owners.

  • Low jitter 800 Mbps fully differential data path
  • 145 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern at 800 Mbps
  • Single +3.3 V Supply
  • Less than 413 mW (typ) total power dissipation
  • Balanced output impedance
  • Output channel-to-channel skew is 35ps (typ)
  • Differential output voltage (VOD) is 320mV (typ) with 100Ω termination load.
  • LVDS receiver inputs accept LVPECL signals
  • Fast propagation delay of 2.8 ns (typ)
  • Receiver input threshold < ±100 mV
  • 28 lead TSSOP package
  • Conforms to ANSI/TIA/EIA-644 LVDS standard

All trademarks are the property of their respective owners.

DS90LV110 is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 400MHz.

The DS90LV110 accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks.

The LVDS outputs can be put into TRI-STATE by use of the enable pin.

For more details, please refer to the Application Information section of this datasheet.

DS90LV110 is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 400MHz.

The DS90LV110 accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks.

The LVDS outputs can be put into TRI-STATE by use of the enable pin.

For more details, please refer to the Application Information section of this datasheet.

Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 2
Type Title Date
* Data sheet DS90LV110T 1 to 10 LVDS Data/Clock Distributor datasheet (Rev. I) 16 Apr 2013
Application note An Overview of LVDS Technology 05 Oct 1998

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

IBIS Model for DS90LV110AT 1 to 10 LVDS Data/Clock Distributor

SNLM152.IBS (92 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 28 Ultra Librarian

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos