홈 마이크로컨트롤러(MCU) 및 프로세서 Arm 기반 프로세서
홈
마이크로컨트롤러(MCU) 및 프로세서
Arm 기반 프로세서

OMAP3515

활성

Sitara 프로세서: Arm Cortex-A8, 3D 그래픽, LPDDR

지금 주문
데이터시트
사용 설명서
정오표

OMAP3515

활성
데이터시트 지금 주문

제품 상세 정보

Arm CPU 1 Arm Cortex-A8 Arm (max) (MHz) 720 Coprocessors GPU CPU 32-bit Graphics acceleration 1 3D Display type 1 LCD Hardware accelerators SGX Graphics Operating system Linux, RTOS Security Cryptography Rating Catalog Power supply solution TPS65921, TPS65950 Operating temperature range (°C) -40 to 105
Arm CPU 1 Arm Cortex-A8 Arm (max) (MHz) 720 Coprocessors GPU CPU 32-bit Graphics acceleration 1 3D Display type 1 LCD Hardware accelerators SGX Graphics Operating system Linux, RTOS Security Cryptography Rating Catalog Power supply solution TPS65921, TPS65950 Operating temperature range (°C) -40 to 105
FCCSP (CBB) 515 144 mm² 12 x 12 FCCSP (CUS) 423 256 mm² 16 x 16
  • OMAP3 Devices:
    • OMAP™ 3 Architecture
    • MPU Subsystem
      • Up to 720-MHz ARM® Cortex™-A8 Core
      • NEON™ SIMD Coprocessor
    • PowerVR® SGX™ Graphics Accelerator
      • Tile-Based Architecture Delivering up to 1 MPoly/sec
      • Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Programmable High-Quality Image Anti-Aliasing
    • Fully Software-Compatible with ARM9™
    • Commercial and Extended Temperature Grades
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • TrustZone®
      • Thumb®-2
      • MMU Enhancements
    • In-Order, Dual-Issue, Superscalar Microprocessor Core
    • NEON Multimedia Architecture
    • Over 2x Performance of ARMv6 SIMD
    • Supports Both Integer and Floating-Point SIMD
    • Jazelle® RCT Execution Environment Architecture
    • Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
    • Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
  • ARM Cortex-A8 Memory Architecture:
    • -KB Instruction Cache (4-Way Set-Associative)
    • -KB Data Cache (4-Way Set-Associative)
    • -KB L2 Cache
  • 112KB of ROM
  • 64KB of Shared SRAM
  • Endianess:
    • ARM Instructions – Little Endian
    • ARM Data – Configurable
  • External Memory Interfaces:
    • General Purpose Memory Controller (GPMC)
      • 16-Bit-Wide Multiplexed Address and Data Bus
      • Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin
      • Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM
      • Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)
      • Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
  • System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
  • Camera Image Signal Processor (ISP)
    • CCD and CMOS Imager Interface
    • Memory Data Input
    • BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface
    • Glueless Interface to Common Video Decoders
    • Resize Engine
      • Resize Images From 1/4x to 4x
      • Separate Horizontal and Vertical Control
  • Display Subsystem
    • Parallel Digital Output
      • Up to 24-Bit RGB
      • HD Maximum Resolution
      • Supports Up to 2 LCD Panels
      • Support for Remote Frame Buffer Interface (RFBI) LCD Panels
    • 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
      • Composite NTSC and PAL Video
      • Luma and Chroma Separate Video (S-Video)
    • Rotation 90-, 180-, and 270-Degrees
    • Resize Images From 1/4x to 8x
    • Color Space Converter
    • 8-Bit Alpha Blending
  • Serial Communication
    • 5 Multichannel Buffered Serial Ports (McBSPs)
      • 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)
      • 5-KB Transmit and Receive Buffer (McBSP2)
      • SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
      • Direct Interface to I2S and PCM Device and TDM Buses
      • 128-Channel Transmit and Receive Mode
    • Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports
    • High-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)
    • High-, Full-, and Low-Speed Multiport USB Host Subsystem
      • 12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface
    • One HDQ™/1-Wire® Interface
    • UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
    • Three Master and Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
  • Removable Media Interfaces:
    • Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
  • Comprehensive Power, Reset, and Clock Management
    • SmartReflex™ Technology
    • Dynamic Voltage and Frequency Scaling (DVFS)
  • Test Interfaces
    • IEEE 1149.1 (JTAG) Boundary-Scan Compatible
    • ETM Interface
    • Serial Data Transport Interface (SDTI)
  • 12 32-Bit General-Purpose Timers
  • 2 32-Bit Watchdog Timers
  • 1 32-Bit 32-kHz Sync Timer
  • Up to General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
  • 5-nm CMOS Technologies
  • Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
  • Discrete Memory Interface
  • Packages:
  • 1.8-V I/O and 3.0-V (MMC1 Only),


    Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.
  • OMAP3 Devices:
    • OMAP™ 3 Architecture
    • MPU Subsystem
      • Up to 720-MHz ARM® Cortex™-A8 Core
      • NEON™ SIMD Coprocessor
    • PowerVR® SGX™ Graphics Accelerator
      • Tile-Based Architecture Delivering up to 1 MPoly/sec
      • Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Programmable High-Quality Image Anti-Aliasing
    • Fully Software-Compatible with ARM9™
    • Commercial and Extended Temperature Grades
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • TrustZone®
      • Thumb®-2
      • MMU Enhancements
    • In-Order, Dual-Issue, Superscalar Microprocessor Core
    • NEON Multimedia Architecture
    • Over 2x Performance of ARMv6 SIMD
    • Supports Both Integer and Floating-Point SIMD
    • Jazelle® RCT Execution Environment Architecture
    • Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
    • Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
  • ARM Cortex-A8 Memory Architecture:
    • -KB Instruction Cache (4-Way Set-Associative)
    • -KB Data Cache (4-Way Set-Associative)
    • -KB L2 Cache
  • 112KB of ROM
  • 64KB of Shared SRAM
  • Endianess:
    • ARM Instructions – Little Endian
    • ARM Data – Configurable
  • External Memory Interfaces:
    • General Purpose Memory Controller (GPMC)
      • 16-Bit-Wide Multiplexed Address and Data Bus
      • Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin
      • Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM
      • Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)
      • Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
  • System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
  • Camera Image Signal Processor (ISP)
    • CCD and CMOS Imager Interface
    • Memory Data Input
    • BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface
    • Glueless Interface to Common Video Decoders
    • Resize Engine
      • Resize Images From 1/4x to 4x
      • Separate Horizontal and Vertical Control
  • Display Subsystem
    • Parallel Digital Output
      • Up to 24-Bit RGB
      • HD Maximum Resolution
      • Supports Up to 2 LCD Panels
      • Support for Remote Frame Buffer Interface (RFBI) LCD Panels
    • 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
      • Composite NTSC and PAL Video
      • Luma and Chroma Separate Video (S-Video)
    • Rotation 90-, 180-, and 270-Degrees
    • Resize Images From 1/4x to 8x
    • Color Space Converter
    • 8-Bit Alpha Blending
  • Serial Communication
    • 5 Multichannel Buffered Serial Ports (McBSPs)
      • 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)
      • 5-KB Transmit and Receive Buffer (McBSP2)
      • SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
      • Direct Interface to I2S and PCM Device and TDM Buses
      • 128-Channel Transmit and Receive Mode
    • Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports
    • High-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)
    • High-, Full-, and Low-Speed Multiport USB Host Subsystem
      • 12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface
    • One HDQ™/1-Wire® Interface
    • UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
    • Three Master and Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
  • Removable Media Interfaces:
    • Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
  • Comprehensive Power, Reset, and Clock Management
    • SmartReflex™ Technology
    • Dynamic Voltage and Frequency Scaling (DVFS)
  • Test Interfaces
    • IEEE 1149.1 (JTAG) Boundary-Scan Compatible
    • ETM Interface
    • Serial Data Transport Interface (SDTI)
  • 12 32-Bit General-Purpose Timers
  • 2 32-Bit Watchdog Timers
  • 1 32-Bit 32-kHz Sync Timer
  • Up to General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
  • 5-nm CMOS Technologies
  • Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
  • Discrete Memory Interface
  • Packages:
  • 1.8-V I/O and 3.0-V (MMC1 Only),


    Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.

devices are based on the enhanced OMAP 3 architecture.

The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:

  • Streaming video
  • Video conferencing
  • High-resolution still image

The device supports high-level operating systems (HLOSs), such as:

  • Linux®
  • Windows® CE
  • Android™

This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.

The following subsystems are part of the device:

  • Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor
  • PowerVR SGX subsystem for 3D graphics acceleration to support display (OMAP35 device only)
  • Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors
  • Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC and PAL video out.
  • Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

  • A comprehensive power- and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex adaptative voltage control. This power-management technique for automatic control of the operating voltage of a module reduces the active power consumption.
  • Memory-stacking feature using the package-on-package (POP) implementation (CBB and CBC packages only)

OMAP35 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences).

This data manual presents the electrical and mechanical specifications for the OMAP35 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP35 applications processors unless otherwise indicated. This data manual consists of the following sections:

  • Section 2: Terminal Description: assignment, electrical characteristics, multiplexing, and functional description
  • Section 3: Electrical Characteristics: power domains, operating conditions, power consumption, and DC characteristics
  • Section 4: Clock Specifications input and output clocks, DPLL and DLL
  • Section 5: Video Dac Specifications
  • Section 6: Timing Requirements and Switching Characteristics
  • Section 7: Package Characteristics: thermal characteristics, device nomenclature, and mechanical data for available packaging

devices are based on the enhanced OMAP 3 architecture.

The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:

  • Streaming video
  • Video conferencing
  • High-resolution still image

The device supports high-level operating systems (HLOSs), such as:

  • Linux®
  • Windows® CE
  • Android™

This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.

The following subsystems are part of the device:

  • Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor
  • PowerVR SGX subsystem for 3D graphics acceleration to support display (OMAP35 device only)
  • Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors
  • Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC and PAL video out.
  • Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

  • A comprehensive power- and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex adaptative voltage control. This power-management technique for automatic control of the operating voltage of a module reduces the active power consumption.
  • Memory-stacking feature using the package-on-package (POP) implementation (CBB and CBC packages only)

OMAP35 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences).

This data manual presents the electrical and mechanical specifications for the OMAP35 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP35 applications processors unless otherwise indicated. This data manual consists of the following sections:

  • Section 2: Terminal Description: assignment, electrical characteristics, multiplexing, and functional description
  • Section 3: Electrical Characteristics: power domains, operating conditions, power consumption, and DC characteristics
  • Section 4: Clock Specifications input and output clocks, DPLL and DLL
  • Section 5: Video Dac Specifications
  • Section 6: Timing Requirements and Switching Characteristics
  • Section 7: Package Characteristics: thermal characteristics, device nomenclature, and mechanical data for available packaging
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이 제품은 새로운 콘텐츠 또는 소프트웨어 업데이트와 같은 새로운 프로젝트에 대한 TI의 지속적인 설계 지원을 받지 않습니다. 가능한 경우 제품 폴더에서 관련 자료, 소프트웨어 및 툴을 확인할 수 있습니다. TI E2ETM 지원 포럼에서 보관된 정보를 검색할 수도 있습니다.

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모두 보기18
유형 직함 날짜
* Data sheet OMAP3515 and OMAP3503 Applications Processors datasheet (Rev. H) 2013/10/10
* Errata OMAP3530/25/15/03 Applications Processor Silicon Errata (Rev. F) 2010/10/12
* User guide OMAP35x Technical Reference Manual (Rev. Y) 2012/12/19
User guide SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 2020/06/01
Application note (Cancelled - see the B revision, create by mistake 14-may-2009) (Rev. C) PDF | HTML 2020/03/03
Application note OMAP3530/25/15/03, DM3730/25, AM3715/03 CBB, CBC and CUS reflow profiles 2019/03/20
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 2018/09/24
Application note PCB Assembly Guidelines for 0.4mm Package-On-Package (PoP) Packages, Part II (Rev. A) 2013/11/01
User guide Delta for OMAP35x Technical Reference Manual Version X to Version Y (Rev. Y) 2012/12/10
Application note PCB Assembly Guidelines for 0.5mm Package-on-Package Apps Processors, Part II 2010/06/23
Application note PCB Design Guidelines for 0.5mm Package-On-Package Apps Processors, Part I 2010/06/23
Application note Migrating from OMAP3530 to AM37x 2010/06/03
Application note Migrating from OMAP3530 to AM35x 2010/05/24
User guide OMAP35x Peripherals Overview Reference Guide (Rev. A) 2010/01/20
Application note OMAP35x Linux PSP Data Sheet 2009/10/16
Design guide Powering OMAP35x with TPS65073x 2009/10/13
Application note Powering OMAP™3 With TPS6235x: Design-In Guide 2008/12/03
Application note OMAP35x 0.65mm Pitch Layout Methods (Rev. B) 2008/06/26

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

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TMDSEMU200-U — XDS200 USB 디버그 프로브

XDS200은 TI 임베디드 디바이스 디버깅에 사용되는 디버그 프로브(에뮬레이터)입니다. XDS200은 저렴한 XDS110 및 고성능 XDS560v2에 비해 저렴한 비용으로 우수한 성능을 균형 있게 제공합니다. 단일 포드에서 광범위한 표준(IEEE1149.1, IEEE1149.7, SWD)을 지원합니다. 모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 Arm® 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 코어 추적의 경우 XDS560v2 PRO TRACE가 (...)

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XDS560v2는 디버그 프로브의 XDS560™ 제품군 중 최고의 성능을 가진 제품으로, 기존의 JTAG 표준(IEEE1149.1)과 cJTAG(IEEE1149.7)를 모두 지원합니다. SWD(직렬 와이어 디버그)는 지원하지 않습니다.

모든 XDS 디버그 프로브는 ETB(Embedded Trace Buffer)를 특징으로 하는 모든 ARM 및 DSP 프로세서에서 코어 및 시스템 추적을 지원합니다. 핀을 통한 추적의 경우 XDS560v2 PRO TRACE가 필요합니다.

XDS560v2는 MIPI HSPT 60핀 커넥터(TI 14핀, (...)

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TMDSEMU560V2STM-UE — XDS560v2 시스템 추적 USB 및 이더넷 디버그 프로브

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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소프트웨어 개발 키트(SDK)

ANDROIDSDK-SITARA — Sitara 마이크로프로세서용 Android 개발 키트

Although originally designed for mobile handsets, the Android Operating System offers designers of embedded applications the ability to easily add a high-level OS to their product. Developed in association with Google, Android delivers a complete operating system  that is ready for (...)
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소프트웨어 개발 키트(SDK)

LINUXDVSDK-OMAP3530 — OMAP3530/3525 디지털 미디어 프로세서용 DVSDK(Linux 디지털 비디오 소프트웨어 개발 키트)

The Linux Digital Video Software Development Kit (DVSDK) enables OMAP35x system integrators to quickly develop Linux-based multimedia applications that can be easily ported across different devices in the OMAP35x generation, including OMAP3530 and OMAP3525 application processors. The DVSDK combines (...)
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소프트웨어 코덱

C64XPLUSCODECS — 코덱 - 비디오 및 음성 - C64x+ 기반 디바이스(OMAP35x, C645x, C647x, DM646, DM644x, DM643x)

TI 코덱은 무료이고 프로덕션 라이선스와 함께 제공되며 지금 다운로드할 수 있습니다. 모두 프로덕션급 테스트를 통해 비디오 및 음성 애플리케이션에 원활하게 통합되는 것으로 확인되었습니다. 소프트웨어 다운로드 버튼(위)을 클릭하면 테스트를 거친 최신 버전의 코덱에 액세스할 수 있습니다. 데이터시트와 릴리스 노트는 해당 페이지와 각 설치 프로그램에 있습니다.

 

 

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소프트웨어 코덱

OMAP35XCODECS — Codecs for OMAP35x - Software and Documentation

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio, video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

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제품
Arm 기반 프로세서
OMAP3503 — Sitara 프로세서: Arm Cortex-A8, LPDDR OMAP3515 — Sitara 프로세서: Arm Cortex-A8, 3D 그래픽, LPDDR OMAP3525 — 애플리케이션 프로세서 OMAP3530 — 애플리케이션 프로세서
다운로드 옵션
소프트웨어 프로그래밍 도구

FLASHTOOL — FlashTool for AM35x, AM37x, DM37x and OMAP35x Devices

Flash Tool is a Windows-based application that can be used to transfer binary images from a host PC to TI Sitara AM35x, AM37x, DM37x and OMAP35x target platforms.


Additional Information:

TI GForge - Welcome to gforge.ti.com

TI E2E Community

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지원되는 제품 및 하드웨어

제품
Arm 기반 프로세서
AM3505 — Sitara 프로세서: Arm Cortex-A8, 비디오 프론트 엔드 AM3517 — Sitara 프로세서: Arm Cortex-A8, 3D 그래픽, 비디오 프론트 엔드 AM3703 — Sitara 프로세서: Arm Cortex-A8, 카메라 AM3715 — Sitara 프로세서: Arm Cortex-A8, 3D 그래픽, 카메라 DM3725 — 디지털 미디어 프로세서 DM3730 — 디지털 미디어 프로세서 OMAP3503 — Sitara 프로세서: Arm Cortex-A8, LPDDR OMAP3515 — Sitara 프로세서: Arm Cortex-A8, 3D 그래픽, LPDDR OMAP3525 — 애플리케이션 프로세서 OMAP3530 — 애플리케이션 프로세서
다운로드 옵션
시뮬레이션 모델

OMAP3515/03 CBB IBIS Model (Rev. A)

SPRM320A.ZIP (1575 KB) - IBIS Model
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시뮬레이션 모델

OMAP3515/03 CBB BSDL Model (Rev. C)

SPRM313C.ZIP (11 KB) - BSDL Model
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시뮬레이션 모델

OMAP3515/03 CBC IBIS Model (Rev. A)

SPRM321A.ZIP (1559 KB) - IBIS Model
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시뮬레이션 모델

OMAP3515/03 CBC BSDL MODEL

SPRM473.ZIP (10 KB) - BSDL Model
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시뮬레이션 모델

OMAP3515/03 CUS BSDL Model (Rev. B)

SPRM312B.ZIP (10 KB) - BSDL Model
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시뮬레이션 모델

OMAP3515/03 CUS IBIS Model (Rev. B)

SPRM319B.ZIP (1537 KB) - IBIS Model
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계산 툴

POWEREST — 전력 예상 툴(PET)

Power Estimation Tool (PET) provides users the ability to gain insight in to the power consumption of select TI processors. The tool includes the ability for the user to choose multiple application scenarios and understand the power consumption as well as how advanced power saving techniques can be (...)
옵션 보기
설계 툴

PROCESSORS-3P-SEARCH — Arm 기반 MPU, arm 기반 MCU 및 DSP 타사 검색 툴

TI는 여러 회사와의 협력을 통해 TI 프로세서를 사용하여 광범위한 소프트웨어, 툴 및 SOM을 제공해서 생산 단계로 가는 속도를 높이고 있습니다. 이 검색 툴을 다운로드하여 타사 솔루션을 빠르게 검색하고 필요에 맞는 올바른 타사를 찾아보세요. 여기에 나열된 소프트웨어, 툴 및 모듈은 텍사스 인스트루먼트가 아닌 독립적인 타사에서 생산 및 관리하고 있습니다.

검색 툴은 다음과 같이 제품 유형별로 분류되어 있습니다.

  • 툴에는 IDE/컴파일러, 디버그 및 추적, 시뮬레이션 및 모델링 소프트웨어, 플래시 프로그래머가 포함되어 있습니다.
  • OS에는 (...)
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회로도

Schematic for PR785: Discrete Power Solution for OMAP3503 & OMAP3515

SLUA480.PDF (129 KB)
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패키지 핀 다운로드
FCCSP (CBB) 515 옵션 보기
FCCSP (CUS) 423 옵션 보기
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

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