This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
(1) Additional temperature ranges are available - contact factory.
|VCC (Min) (V)|
|VCC (Max) (V)|
|Voltage (Nom) (V)|
|F @ Nom Voltage (Max) (Mhz)|
|ICC @ Nom Voltage (Max) (mA)|
|tpd @ Nom Voltage (Max) (ns)|
|IOL (Max) (mA)|
|Operating Temperature Range (C)|
|Package Size: mm2:W x L (PKG)|
|HiRel Enhanced Product|
|-55 to 115|
|5SC70: 4 mm2: 2.1 x 2(SC70)|