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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADC08DJ3200

現行

8 位元、雙 3.2-GSPS 或單 6.4-GSPS、射頻取樣類比轉數位轉換器 (ADC)

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產品規格表

ADC08DJ3200

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 8 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2800 Architecture Folding Interpolating SNR (dB) 49.4 ENOB (bit) 7.8 SFDR (dB) 69 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 8 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 8000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2800 Architecture Folding Interpolating SNR (dB) 49.4 ENOB (bit) 7.8 SFDR (dB) 69 Operating temperature range (°C) -40 to 85 Input buffer Yes
FCCSP (AAV) 144 100 mm² 10 x 10
  • ADC core:
    • 8-bit resolution
    • Up to 6.4 GSPS in single-channel mode
    • Up to 3.2 GSPS in dual-channel mode
  • Performance specifications (fIN = 997 MHz):
    • ENOB: 7.8 bits
    • SFDR:
      • Dual-channel mode: 67 dBFS
      • Single-channel mode: 62 dBFS
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 8.0 GHz
    • Usable input frequency range: >10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
    • Analog input common-mode (VICM): 0 V
  • Noiseless aperture delay (TAD) adjustment:
    • Precise sampling control: 19-fs step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B serial data interface:
    • Supports subclass 0 and 1
    • Maximum lane rate: 12.8 Gbps
    • Up to 16 lanes allows reduced lane rate
  • Power consumption: 2.8 W
  • Power supplies: 1.1 V, 1.9 V
  • ADC core:
    • 8-bit resolution
    • Up to 6.4 GSPS in single-channel mode
    • Up to 3.2 GSPS in dual-channel mode
  • Performance specifications (fIN = 997 MHz):
    • ENOB: 7.8 bits
    • SFDR:
      • Dual-channel mode: 67 dBFS
      • Single-channel mode: 62 dBFS
  • Buffered analog inputs with VCMI of 0 V:
    • Analog input bandwidth (–3 dB): 8.0 GHz
    • Usable input frequency range: >10 GHz
    • Full-scale input voltage (VFS, default): 0.8 VPP
    • Analog input common-mode (VICM): 0 V
  • Noiseless aperture delay (TAD) adjustment:
    • Precise sampling control: 19-fs step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B serial data interface:
    • Supports subclass 0 and 1
    • Maximum lane rate: 12.8 Gbps
    • Up to 16 lanes allows reduced lane rate
  • Power consumption: 2.8 W
  • Power supplies: 1.1 V, 1.9 V

The ADC08DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC08DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC08DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. At 5 GSPS, only four total lanes are required running at 12.5 Gbps or 16 lanes can be used to reduce the lane rate to 3.125 Gbps. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications.

The ADC08DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC08DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC08DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. At 5 GSPS, only four total lanes are required running at 12.5 Gbps or 16 lanes can be used to reduce the lane rate to 3.125 Gbps. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications.
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類型 標題 日期
* Data sheet ADC08DJ3200 6.4-GSPS Single-Channel or 3.2-GSPS Dual-Channel, 8-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. A) PDF | HTML 2019年 2月 21日
Application notes Intel Stratix 10 GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design 2018年 5月 30日
EVM User's guide ADCxxDJxx00 Evaluation Module User's Guide (Rev. A) 2018年 1月 9日

設計與開發

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開發板

ADC08DJ3200EVM — ADC08DJ3200 8 位元、雙路 3.2-GSPS 或單路 6.4-GSPS、射頻取樣 ADC 評估模組

ADC08DJ3200 評估模組 (EVM) 可用於評估 ADC08DJ3200 裝置。ADC08DJ3200 是一款低功耗、8 位元、雙通道 3.2-GSPS 或單通道 6.4-GSPS、具有緩衝類比輸入的射頻取樣類比轉數位轉換器 (ADC)，它具有 JESD204B 介面，是具備可編程數值控制振盪器 NCO 和降取設定的整合式數位降壓轉換器。

該 ADC08JD3200EVM 具有變壓器耦合類比輸入，可適應廣泛的訊號來源和頻率。EVM 隨附 LMX2582 時鐘合成器和 LMK04828 JESD204B 時鐘產生器，可配置為提供適用於完整 JESD204B 子類別 1 (...)

使用指南: PDF
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韌體

TI-JESD204-IP — JESD204 快速設計 IP，適用連接到 TI 高速資料轉換器的 FPGA

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
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開發模組 (EVM) 的 GUI

SLAC745 — ADC12DJxx00 GUI

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產品
高速 ADC (≥10 MSPS)
ADC08DJ3200 — 8 位元、雙 3.2-GSPS 或單 6.4-GSPS、射頻取樣類比轉數位轉換器 (ADC) ADC12DJ3200 — 12 位元、雙 3.2-GSPS 或單 6.4-GSPS、射頻取樣類比轉數位轉換器 (ADC)
硬體開發
開發板
ADC08DJ3200EVM — ADC08DJ3200 8 位元、雙路 3.2-GSPS 或單路 6.4-GSPS、射頻取樣 ADC 評估模組 ADC12DJ2700EVM — ADC12DJ2700 12 位元雙路 2.7 GSPS 或單路 5.4 GSPS 射頻取樣 ADC 評估模組 ADC12DJ3200EVM — ADC12DJ3200 12 位元雙路 3.2 GSPS 或單路 6.4 GSPS 射頻取樣 ADC 評估模組
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模擬型號

ADC12DJ3200 IBIS Model

SLVMC42.ZIP (36 KB) - IBIS Model
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模擬型號

ADC12DJ3200 IBIS-AMI Model

SLVMC55.ZIP (5569 KB) - IBIS-AMI Model
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計算工具

FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel Calculator

This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of (...)

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高速 ADC (≥10 MSPS)
ADC08DJ3200 — 8 位元、雙 3.2-GSPS 或單 6.4-GSPS、射頻取樣類比轉數位轉換器 (ADC) ADC12DJ2700 — 12 位元、雙 2.7-GSPS 或單 5.4-GSPS、射頻取樣類比轉數位轉換器 (ADC) ADC12DJ3200 — 12 位元、雙 3.2-GSPS 或單 6.4-GSPS、射頻取樣類比轉數位轉換器 (ADC) ADC12DJ5200RF — 具有雙通道 5.2 GSPS 或單通道 10.4 GSPS 的射頻取樣 12 位元 ADC ADC12J1600 — 12 位元、1.6-GSPS、射頻取樣類比轉數位轉換器 (ADC) ADC12J2700 — 12 位元、2.7-GSPS、射頻取樣類比轉數位轉換器 (ADC) ADC12J4000 — 12 位元、4.0-GSPS、RF 取樣類比轉數位轉換器 (ADC) ADC31RF80 — 14 位元、3-GSPS、RF 取樣寬頻接收器和回饋 IC ADC32RF42 — 雙通道、14 位元、1.5-GSPS 射頻取樣類比轉數位轉換器 (ADC) ADC32RF44 — 雙通道、14 位元、2.6-GSPS 射頻取樣類比轉數位轉換器 (ADC) ADC32RF45 — 雙通道、14 位元、3-GSPS、射頻取樣類比轉數位轉換器 (ADC)
射頻取樣收發器
AFE7422 — 2 發射、2 接收射頻取樣收發器，10MHz 至 6-GHz、最大 1200MHz IBW AFE7444 — 4 發射、4 接收射頻取樣收發器，10MHz 至 6-GHz、最大 600MHz IBW
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模擬工具

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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參考設計

TIDA-01021 — 適用於 DSO、雷達和 5G 無線測試儀的多通道 JESD204B 15 GHz 時鐘參考設計

High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01022 — 適用於 DSO、雷達和 5G 無線測試系統的靈活 3.2-GSPS 多通道 AFE 參考設計

This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew (...)
Design guide: PDF
電路圖: PDF
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