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射頻取樣收發器

AFE7444

現行

4 發射、4 接收射頻取樣收發器，10MHz 至 6-GHz、最大 600MHz IBW

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產品規格表

AFE7444

現行
產品規格表 立即訂購

產品詳細資料

Applications General purpose Number of TXs and RXs 4 TX Number of DUCs per TX 2 Number of DDCs per RX 2 RF frequency (max) (MHz) 6000 RF frequency (min) (MHz) 10 Operating temperature range (°C) -40 to 85 Rating Catalog
Applications General purpose Number of TXs and RXs 4 TX Number of DUCs per TX 2 Number of DDCs per RX 2 RF frequency (max) (MHz) 6000 RF frequency (min) (MHz) 10 Operating temperature range (°C) -40 to 85 Rating Catalog
FCBGA (ABJ) 400 289 mm² 17 x 17 FCBGA (ALK) 400 289 mm² 17 x 17
  • Four, 14-bit, 9-GSPS DACs
    • Up to 800-MHz signal bandwidth
    • 1 DSA per channel tunes output power
  • Four, 14-Bit, 3-GSPS ADCs
    • Up to 800-MHz signal bandwidth
    • NSD: –151 dBFS/Hz
    • AC performance at fIN = 2.6 GHz, –3 dBFS
      • SNR: 55 dBFS
      • SFDR: 73 dBc HD2 and HD3
      • SFDR: 91 dBc worst spur
    • 2 DSA per channel extends dynamic range
    • RF and digital power detectors
  • RF frequency range: 10 MHz to 6 GHz
  • Fast frequency hopping < 1 µs
  • Receive digital signal path:
    • dual DDC per ADC
    • 3-phase coherent 32-bit NCOs per DDC
    • Decimation ratio: 3x to 32x
  • Transmit digital signal path:
    • Dual DUC per DAC with 32-bit NCOs
    • Interpolation ratio: 8x to 36x
    • Sin(x)/x correction and configurable delay
    • Power amplifier protection (PAP)
  • JESD204B interface:
    • 8 transceivers at up to 15 Gbps
    • Subclass 1 multichip synchronization
  • Clocks:
    • Internal PLL and VCO with bypass option
    • Clock output up to 3 GHz with clock divider
  • DAC power dissipation: 1.7 W/ch at 9 GSPS
  • ADC power dissipation: 1.8 W/ch at 3 GSPS
  • Package: 17-mm x 17-mm FC BGA, 0.8-mm pitch
  • Four, 14-bit, 9-GSPS DACs
    • Up to 800-MHz signal bandwidth
    • 1 DSA per channel tunes output power
  • Four, 14-Bit, 3-GSPS ADCs
    • Up to 800-MHz signal bandwidth
    • NSD: –151 dBFS/Hz
    • AC performance at fIN = 2.6 GHz, –3 dBFS
      • SNR: 55 dBFS
      • SFDR: 73 dBc HD2 and HD3
      • SFDR: 91 dBc worst spur
    • 2 DSA per channel extends dynamic range
    • RF and digital power detectors
  • RF frequency range: 10 MHz to 6 GHz
  • Fast frequency hopping < 1 µs
  • Receive digital signal path:
    • dual DDC per ADC
    • 3-phase coherent 32-bit NCOs per DDC
    • Decimation ratio: 3x to 32x
  • Transmit digital signal path:
    • Dual DUC per DAC with 32-bit NCOs
    • Interpolation ratio: 8x to 36x
    • Sin(x)/x correction and configurable delay
    • Power amplifier protection (PAP)
  • JESD204B interface:
    • 8 transceivers at up to 15 Gbps
    • Subclass 1 multichip synchronization
  • Clocks:
    • Internal PLL and VCO with bypass option
    • Clock output up to 3 GHz with clock divider
  • DAC power dissipation: 1.7 W/ch at 9 GSPS
  • ADC power dissipation: 1.8 W/ch at 3 GSPS
  • Package: 17-mm x 17-mm FC BGA, 0.8-mm pitch

The AFE7444 is a quad-channel, wideband, RF-sampling analog front end (AFE) based on 14-bit, 9-GSPS DACs and 14-bit, 3-GSPS ADCs. With operation at an RF of up to 6 GHz, this device enables direct RF sampling into the C-band frequency range without the need for additional frequency conversions stages. This improvement in density and flexibility enables high-channel-count, multimission systems.

The DAC signal paths support interpolation and digital up conversion options that deliver up to 800 MHz of signal bandwidth. The differential output path includes a digital step attenuator (DSA), which enables tuning of output power.

Each ADC input path includes a dual DSA and RF and Digital power detectors. Flexible decimation options provide optimization of data bandwidth.

An 8-lane (8 TX + 8 RX) subclass-1 compliant JESD204B interface operates at up to 15 Gbps. A bypassable on-chip PLL simplifies clock operation with an optional clock output.

The AFE7444 is a quad-channel, wideband, RF-sampling analog front end (AFE) based on 14-bit, 9-GSPS DACs and 14-bit, 3-GSPS ADCs. With operation at an RF of up to 6 GHz, this device enables direct RF sampling into the C-band frequency range without the need for additional frequency conversions stages. This improvement in density and flexibility enables high-channel-count, multimission systems.

The DAC signal paths support interpolation and digital up conversion options that deliver up to 800 MHz of signal bandwidth. The differential output path includes a digital step attenuator (DSA), which enables tuning of output power.

Each ADC input path includes a dual DSA and RF and Digital power detectors. Flexible decimation options provide optimization of data bandwidth.

An 8-lane (8 TX + 8 RX) subclass-1 compliant JESD204B interface operates at up to 15 Gbps. A bypassable on-chip PLL simplifies clock operation with an optional clock output.
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類型 標題 日期
* Data sheet AFE7444 Quad-channel, RF-sampling AFE with 14-bit, 9-GSPS DACs and 14-bit, 3-GSPS ADCs datasheet (Rev. A) PDF | HTML 2019年 1月 25日
Application brief An Efficient PoL Power Supply Design for High-Speed Data Converters PDF | HTML 2020年 9月 29日
Application note AFE74xx Power Dissipation Comparison Across Modes 2019年 12月 7日
Application note Temp Profile to Maintain Optimum FIT Performance 2019年 7月 23日
Technical article How to achieve fast frequency hopping PDF | HTML 2019年 3月 3日
Application note AFE74xx as a single-chip wideband repeater using loopback mode PDF | HTML 2019年 1月 29日
Application note Evaluating the frequency hopping capability of the AFE74xx PDF | HTML 2018年 12月 3日
EVM User's guide AFE7444EVM and AFE7422EVM User's Guide 2018年 10月 10日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

韌體

TI-JESD204-IP — JESD204 快速設計 IP，適用連接到 TI 高速資料轉換器的 FPGA

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
要求
計算工具

FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel Calculator

This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of (...)

支援產品和硬體

支援產品和硬體

產品
接收器
ADC32RF80 — 雙通道、14 位元、3-GSPS、雙 DDC/通道、RF 取樣寬頻接收器和回饋 IC ADC32RF82 — 雙通道、14 位元、2.45-GSPS、射頻取樣電信接收器和回饋 IC ADC32RF83 — 雙通道、14 位元、3-GSPS、單 DDC/通道、射頻取樣寬頻接收器和回饋 IC
高速 ADC (≥10 MSPS)
ADC08DJ3200 — 8 位元、雙 3.2-GSPS 或單 6.4-GSPS、射頻取樣類比轉數位轉換器 (ADC) ADC12DJ2700 — 12 位元、雙 2.7-GSPS 或單 5.4-GSPS、射頻取樣類比轉數位轉換器 (ADC) ADC12DJ3200 — 12 位元、雙 3.2-GSPS 或單 6.4-GSPS、射頻取樣類比轉數位轉換器 (ADC) ADC12DJ5200RF — 具有雙通道 5.2 GSPS 或單通道 10.4 GSPS 的射頻取樣 12 位元 ADC ADC12J1600 — 12 位元、1.6-GSPS、射頻取樣類比轉數位轉換器 (ADC) ADC12J2700 — 12 位元、2.7-GSPS、射頻取樣類比轉數位轉換器 (ADC) ADC12J4000 — 12 位元、4.0-GSPS、RF 取樣類比轉數位轉換器 (ADC) ADC31RF80 — 14 位元、3-GSPS、RF 取樣寬頻接收器和回饋 IC ADC32RF42 — 雙通道、14 位元、1.5-GSPS 射頻取樣類比轉數位轉換器 (ADC) ADC32RF44 — 雙通道、14 位元、2.6-GSPS 射頻取樣類比轉數位轉換器 (ADC) ADC32RF45 — 雙通道、14 位元、3-GSPS、射頻取樣類比轉數位轉換器 (ADC)
射頻取樣收發器
AFE7422 — 2 發射、2 接收射頻取樣收發器，10MHz 至 6-GHz、最大 1200MHz IBW AFE7444 — 4 發射、4 接收射頻取樣收發器，10MHz 至 6-GHz、最大 600MHz IBW
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參考設計

TIDA-010132 — 適合於雷達和電子戰應用的多通道射頻收發器參考設計

This reference design, an 8-channel analog front end (AFE), is demonstrated using two AFE7444 4-channel RF transceivers and a LMK04828-LMX2594 based clocking subsystem which can enable designs to scale to 16 or more channels. Each AFE channel consists of a 14-bit, 9-GSPS DAC and a 3-GSPS ADC that (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-010131 — 適用於雷達和無線 5G 測試儀的多通道射頻收發器計時參考設計

Analog front end for high-speed end equipments like phased-array radars, wireless communication testers, and electronic warfare require synchronized, multipletransceiver signal chains. Each transceiver signal chain includes high-speed, analog-to-digital converters (ADCs), digital-to-analog (...)
Design guide: PDF
電路圖: PDF
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