產品詳細資料

Sample rate (max) (Msps) 1500 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 3200 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 1.35 Power consumption (typ) (mW) 4000 Architecture Pipeline SNR (dB) 63 ENOB (bit) 9.9 SFDR (dB) 70 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 1500 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 3200 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 1.35 Power consumption (typ) (mW) 4000 Architecture Pipeline SNR (dB) 63 ENOB (bit) 9.9 SFDR (dB) 70 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (RMP) 72 100 mm² 10 x 10
  • 14-Bit, Dual-Channel, 1.5-GSPS ADC
  • Noise Floor: –151.8 dBFS/Hz
  • RF Input Supports Up to 4 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 950 MHz, –2 dBFS):
    • SNR: 61.1 dBFS
    • SFDR: 67-dBc HD2, HD3
  • Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
    • SNR: 58.9 dBFS
    • SFDR: 64-dBc HD2, HD3
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors With Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel Up to 12.5 Gbps
  • Power Dissipation: 2 W/Ch at 1.5 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • 14-Bit, Dual-Channel, 1.5-GSPS ADC
  • Noise Floor: –151.8 dBFS/Hz
  • RF Input Supports Up to 4 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 950 MHz, –2 dBFS):
    • SNR: 61.1 dBFS
    • SFDR: 67-dBc HD2, HD3
  • Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
    • SNR: 58.9 dBFS
    • SFDR: 64-dBc HD2, HD3
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors With Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel Up to 12.5 Gbps
  • Power Dissipation: 2 W/Ch at 1.5 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)

The ADC32RF42 device is a 14-bit, 1.5-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF42 delivers a noise spectral density of –151.8 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF42 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).



The ADC32RF42 device is a 14-bit, 1.5-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF42 delivers a noise spectral density of –151.8 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF42 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).



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* Data sheet ADC32RF42 Dual-Channel, 14-Bit, 1.5-GSPS, Analog-to-Digital Converter datasheet PDF | HTML 2017年 5月 16日
EVM User's guide ADC32RFxxEVM User's Guide (Rev. E) 2020年 1月 31日
Application note Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B) 2017年 9月 5日

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開發板

ADC32RF42EVM — ADC32RF42 雙通道 14 位元 1.5 GSPS 射頻取樣 ADC 評估模組

ADC32RF42 評估模組 (EVM) 展示了具有 JESD204B 介面的雙 1.5-GSPS 14 位元類比轉數位轉換器 (ADC) 的性能。此 EVM 包含 ADC32RF42 裝置,而且 LMK04828 與TI 電壓穩壓器會提供 JESD204B 時鐘計時功能,以提供必要的電壓。

ADC 各通道的輸入預設連接至變壓器輸入電路,其可連接至 50-Ω 單端訊號來源。時鐘參考輸入可透過變壓器輸入提供,並可連接至 50-Ω 單端時鐘來源。板載 LMK04828 可用於產生必要的 JESD204B 時鐘。透過板載 USB 連線和 Windows® 版 GUI (...)

使用指南: PDF
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韌體

TI-JESD204-IP — JESD204 快速設計 IP,適用連接到 TI 高速資料轉換器的 FPGA

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
開發模組 (EVM) 的 GUI

SBAC148 ADC32RFxxEVM SPI GUI Installer

lock = 需要匯出核准 (1 分鐘)
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產品
接收器
ADC32RF80 雙通道、14 位元、3-GSPS、雙 DDC/通道、RF 取樣寬頻接收器和回饋 IC ADC32RF82 雙通道、14 位元、2.45-GSPS、射頻取樣電信接收器和回饋 IC
高速 ADC (≥10 MSPS)
ADC32RF42 雙通道、14 位元、1.5-GSPS 射頻取樣類比轉數位轉換器 (ADC) ADC32RF44 雙通道、14 位元、2.6-GSPS 射頻取樣類比轉數位轉換器 (ADC) ADC32RF45 雙通道、14 位元、3-GSPS、射頻取樣類比轉數位轉換器 (ADC)
硬體開發
開發板
ADC32RF42EVM ADC32RF42 雙通道 14 位元 1.5 GSPS 射頻取樣 ADC 評估模組 ADC32RF44EVM ADC32RF44 雙通道、14 位元、2.6 GSPS、射頻取樣 ADC 評估模組 ADC32RF45EVM 適用於雙通道、14 位元、3-GSPS、射頻取樣 ADC 的 ADC32RF45 評估模組 ADC32RF80EVM 適用於雙通道、14 位元、3-GSPS、射頻取樣寬頻接收器的 ADC32RF80 評估模組 ADC32RF82EVM ADC32RF82 雙通道、14 位元、2.45 GSPS、射頻取樣電信接收器評估模組
模擬型號

ADC32RF45 IBIS Model

SBAM273.ZIP (46 KB) - IBIS Model
模擬型號

ADC32RF45 IBIS-AMI Model

SBAM274.ZIP (3109 KB) - IBIS-AMI Model
計算工具

FREQ-DDC-FILTER-CALC RF-Sampling Frequency Planner, Analog Filter, and DDC Excel Calculator

This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.

In the concept phase, a frequency-planning tool enables fine tuning of (...)

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產品
接收器
ADC32RF80 雙通道、14 位元、3-GSPS、雙 DDC/通道、RF 取樣寬頻接收器和回饋 IC ADC32RF82 雙通道、14 位元、2.45-GSPS、射頻取樣電信接收器和回饋 IC ADC32RF83 雙通道、14 位元、3-GSPS、單 DDC/通道、射頻取樣寬頻接收器和回饋 IC
高速 ADC (≥10 MSPS)
ADC08DJ3200 8 位元、雙 3.2-GSPS 或單 6.4-GSPS、射頻取樣類比轉數位轉換器 (ADC) ADC12DJ2700 12 位元、雙 2.7-GSPS 或單 5.4-GSPS、射頻取樣類比轉數位轉換器 (ADC) ADC12DJ3200 12 位元、雙 3.2-GSPS 或單 6.4-GSPS、射頻取樣類比轉數位轉換器 (ADC) ADC12DJ5200RF 具有雙通道 5.2 GSPS 或單通道 10.4 GSPS 的射頻取樣 12 位元 ADC ADC12J1600 12 位元、1.6-GSPS、射頻取樣類比轉數位轉換器 (ADC) ADC12J2700 12 位元、2.7-GSPS、射頻取樣類比轉數位轉換器 (ADC) ADC12J4000 12 位元、4.0-GSPS、RF 取樣類比轉數位轉換器 (ADC) ADC31RF80 14 位元、3-GSPS、RF 取樣寬頻接收器和回饋 IC ADC32RF42 雙通道、14 位元、1.5-GSPS 射頻取樣類比轉數位轉換器 (ADC) ADC32RF44 雙通道、14 位元、2.6-GSPS 射頻取樣類比轉數位轉換器 (ADC) ADC32RF45 雙通道、14 位元、3-GSPS、射頻取樣類比轉數位轉換器 (ADC)
射頻取樣收發器
AFE7422 2 發射、2 接收射頻取樣收發器,10MHz 至 6-GHz、最大 1200MHz IBW AFE7444 4 發射、4 接收射頻取樣收發器,10MHz 至 6-GHz、最大 600MHz IBW
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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