現在提供此產品的更新版本
引腳對引腳的功能與所比較的產品相同
UCC21530-Q1
- AEC-Q100 qualified with:
- Device temperature grade 1
- Device HBM ESD classification level H2
- Device CDM ESD classification level C6
- Functional Safety Quality-Managed
- Universal: dual low-side, dual high-side or half-bridge driver
- Wide body SOIC-14 (DWK) package
- 3.3-mm spacing between driver channels
- Switching parameters:
- 19-ns typical propagation delay
- 10-ns minimum pulse width
- 5-ns maximum delay matching
- 6-ns maximum pulse-width distortion
- Common-mode transient immunity (CMTI) greater than 100-V/ns
- Isolation barrier life >40 years
- 4-A peak source, 6-A peak sink output
- TTL and CMOS compatible inputs
- 3-V to 18-V input VCCI range
- Up to 25-V VDD output drive supply
- 8-V and 12-V VDD UVLO options
- Programmable overlap and dead time
- Rejects input pulses and noise transients shorter than 5 ns
- Operating temperature range –40 to +125°C
- Safety-related certifications:
- 8000-VPK isolation per DIN V VDE V 0884-11 :2017-01
- 5.7-kVRMS isolation for 1 minute per UL 1577
- CSA certification per IEC 60950-1, IEC 62368-1, IEC 61010-1 and IEC 60601-1 end equipment standards
- CQC certification per GB4943.1-2011
The UCC21530-Q1 is an isolated dual-channel gate driver with 4-A source and 6-A sink peak current. It is designed to drive IGBTs, Si MOSFETs, and SiC MOSFETs up to 5-MHz with best-in-class propagation delay and pulse-width distortion.
The input side is isolated from the two output drivers by a 5.7-kVRMS reinforced isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI). Internal functional isolation between the two secondary-side drivers allows a working voltage of up to 1850 V.
This driver can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver with programmable dead time (DT). The EN pin pulled low shuts down both outputs simultaneously and allows for normal operation when left open or pulled high. As a fail-safe measure, primary-side logic failures force both outputs low.
The device accepts VDD supply voltages up to 25 V. A wide input VCCI range from 3 V to 18 V makes the driver suitable for interfacing with both analog and digital controllers. All the supply voltage pins have under voltage lock-out (UVLO) protection.
要求更多資訊
UCC21530-Q1 安全手冊和安全適配率報告現已發行。請立即索取
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | UCC21530-Q1 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver with 3.3-mm Channel-to-Channel Spacing datasheet (Rev. D) | PDF | HTML | 2021年 4月 29日 |
Certificate | VDE Certificate for Reinforced Isolation for DIN EN IEC 60747-17 (Rev. S) | 2024年 2月 29日 | ||
White paper | 以可靠且經濟實惠的隔離技術解決高電壓設計挑戰 (Rev. C) | PDF | HTML | 2024年 2月 15日 | |
Application note | Impact of Narrow Pulse Widths in Gate Driver Circuits (Rev. A) | PDF | HTML | 2024年 1月 25日 | |
Certificate | UCC21540 CQC Certificate of Product Certification | 2023年 8月 17日 | ||
Certificate | UCC215xx CQC Certificate of Product Certification | 2023年 8月 17日 | ||
Certificate | UL Certification E181974 Vol 4. Sec 7 (Rev. C) | 2022年 12月 2日 | ||
Application brief | The Use and Benefits of Ferrite Beads in Gate Drive Circuits | PDF | HTML | 2021年 12月 16日 | |
Certificate | CSA Product Certificate (Rev. A) | 2019年 8月 15日 | ||
Technical article | Searching for the newest innovations in power? Find them at APEC | PDF | HTML | 2019年 2月 9日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
UCC21530EVM-286 — UCC21530 隔離式雙通道驅動器評估模組
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TIDM-02009 — 經 ASIL D 安全概念評估的高速牽引、雙向 DC/DC 轉換參考設計
TIDA-01605 — 具有二級關閉保護功能的車用雙通道 SiC MOSFET 閘極驅動器參考設計
TIDM-02002 — 適用於 HEV/EV 車載充電器的雙向 CLLLC 共振雙主動橋式 (DAB) 參考設計
TIDM-02012 — 採用 MathWorks® 的高電壓 HEV/EV HVAC eCompressor 馬達控制參考設計
MathWorks (...)
PMP21999 — 使用 PCB 繞組變壓器的 6.6 kW、雙向 CLLLC 共振轉換器參考設計
PMP21561 — 安全隔離次級 SiC MOSFET 驅動器參考設計
PMP21553 — 安全隔離主要 SiC MOSFET 驅動器參考設計
封裝 | 引腳 | 下載 |
---|---|---|
SOIC (DWK) | 14 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。