SNVSA18C April   2014  – August 2014 ADC16DX370

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Converter Performance Characteristics
    6. 6.6  Power Supply Electrical Characteristics
    7. 6.7  Analog Interface Electrical Characteristics
    8. 6.8  CLKIN, SYSREF, SYNCb Interface Electrical Characteristics
    9. 6.9  Serial Data Output Interface Electrical Characteristics
    10. 6.10 Digital Input Electrical Interface Characteristics
    11. 6.11 Timing Requirements
    12. 6.12 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Over-Range Functional Characteristics
    2. 7.2 Input Clock Divider and Clock Phase Adjustment Functional Characteristics
    3. 7.3 JESD204B Interface Functional Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Amplitude and Phase Imbalance Correction of Differential Analog Input
      2. 8.3.2  DC Offset Correction
      3. 8.3.3  Over-Range Detection
      4. 8.3.4  Input Clock Divider
      5. 8.3.5  SYSREF Offset Feature and Detection Gate
      6. 8.3.6  Sampling Instant Phase Adjustment
      7. 8.3.7  Serial Differential Output Drivers
        1. 8.3.7.1 De-Emphasis Equalization
      8. 8.3.8  ADC Core Calibration
      9. 8.3.9  Data Format
      10. 8.3.10 JESD204B Supported Features
      11. 8.3.11 Transport Layer Configuration
        1. 8.3.11.1 Lane Configuration
        2. 8.3.11.2 Frame Format
        3. 8.3.11.3 ILA Information
      12. 8.3.12 Test Pattern Sequences
      13. 8.3.13 JESD204B Link Initialization
      14. 8.3.14 SPI
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down and Sleep Modes
    5. 8.5 Register Map
      1. 8.5.1 Register Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input Considerations
        1. 9.1.1.1 Differential Analog Inputs and Full Scale Range
        2. 9.1.1.2 Analog Input Network Model
        3. 9.1.1.3 Input Bandwidth
        4. 9.1.1.4 Driving the Analog Input
        5. 9.1.1.5 Clipping and Over-Range
      2. 9.1.2 CLKIN, SYSREF, and SYNCb Input Considerations
        1. 9.1.2.1 Driving the CLKIN+ and CLKIN- Input
        2. 9.1.2.2 Clock Noise and Edge Rate
        3. 9.1.2.3 Driving the SYSREF Input
        4. 9.1.2.4 SYSREF Signaling
        5. 9.1.2.5 SYSREF Timing
        6. 9.1.2.6 Effectively Using the SYSREF Offset and Detection Gate Features
        7. 9.1.2.7 Driving the SYNCb Input
      3. 9.1.3 Output Serial Interface Considerations
        1. 9.1.3.1 Output Serial-Lane Interface
        2. 9.1.3.2 Voltage Swing and De-Emphasis Optimization
        3. 9.1.3.3 Minimizing EMI
      4. 9.1.4 JESD204B System Considerations
        1. 9.1.4.1 Frame and LMFC Clock Alignment Procedure
        2. 9.1.4.2 Link Interruption
        3. 9.1.4.3 Synchronization Requests and SYNCb Alignment in Multi-Device Systems
        4. 9.1.4.4 Clock Configuration Examples
        5. 9.1.4.5 Configuring the JESD204B Receiver
      5. 9.1.5 SPI
    2. 9.2 Typical Application
      1. 9.2.1 High-IF Sampling Receiver
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Design Procedure
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Design
    2. 10.2 Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Specification Definitions
      2. 12.1.2 JESD204B Definitions
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

The design of the PCB is critical to achieve the full performance of the ADC16DX370 device. Defining the PCB stackup should be the first step in the board design. Experience has shown that at least 6 layers are required to adequately route all required signals to and from the device. Each signal routing layer must have an adjacent solid ground plane to control signal return paths to have minimal loop areas and to achieve controlled impedances for microstrip and stripline routing. Power planes must also have adjacent solid ground planes to control supply return paths. Minimizing the spacing between supply and ground planes improves performance by increasing the distributed decoupling. The recommended stack-up for a 6-layer board design is shown in Figure 57.

Although the ADC16DX370 device consists of both analog and digital circuitry, TI highly recommends solid ground planes that encompass the device and its input and output signal paths. TI does not recommend split ground planes that divide the analog and digital portions of the device. Split ground planes may improve performance if a nearby, noisy, digital device is corrupting the ground reference of the analog signal path. When split ground planes are employed, one must carefully control the supply return paths and keep the paths on top of their respective ground reference planes.

Quality analog input signal and clock signal path layout is required for full dynamic performance. Symmetry of the differential signal paths and discrete components in the path is mandatory and symmetrical shunt-oriented components should have a common grounding via. The high frequency requirements of the input and clock signal paths necessitate using differential routing with controlled impedances and minimizing signal path stubs (including vias) when possible.

Coupling onto or between the clock and input signal paths must be avoided using any isolation techniques available including distance isolation, orientation planning to prevent field coupling of components like inductors and transformers, and providing well coupled reference planes. Via stitching around the clock signal path and the input analog signal path provides a quiet ground reference for the critical signal paths and reduces noise coupling onto these paths. Sensitive signal traces must not cross other signal traces or power routing on adjacent PCB layers, rather a ground plane must separate the traces. If necessary, the traces should cross at 90° angles to minimize crosstalk.

The substrate dielectric materials of the PCB are largely influenced by the speed and length of the high speed serial lanes. The affordable and common FR4 variety may not offer the consistency or loss to support the highest speed transmission (> 5 Gb/s) and long lengths (> 4 inch). Although the VOD and DEM features are available to improve the signal integrity of the serial lanes, some of the highest performing applications may still require special dielectric materials such as Rogers 4350.

Coupling of ambient signals into the signal path is reduced by providing quiet, close reference planes and by maintaining signal path symmetry to ensure the coupled noise is common-mode. Faraday caging may be used in very noisy environments and high dynamic range applications to isolate the signal path.

11.2 Layout Example

ADC16DX370 PCB_Stackup.gif Figure 57. Recommended PCB Layer Stack-Up for a Six-Layer Board

Additional layout examples can be found on the associated EVM tools web page on www.ti.com.

11.3 Thermal Considerations

The exposed thermal pad of the ADC16DX370 device draws heat from the silicon down into the PCB to prevent overheating and must attach to the landing pad with a quality solder connection to maximize thermal conductivity. Overly hot operating temperatures may be alleviated further by increasing the PCB size, filling surface layers with ground planes to increase heat radiation, or using a thermally conductive connection between the package top and a heat sink.