SNVSA18C April   2014  – August 2014 ADC16DX370

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Converter Performance Characteristics
    6. 6.6  Power Supply Electrical Characteristics
    7. 6.7  Analog Interface Electrical Characteristics
    8. 6.8  CLKIN, SYSREF, SYNCb Interface Electrical Characteristics
    9. 6.9  Serial Data Output Interface Electrical Characteristics
    10. 6.10 Digital Input Electrical Interface Characteristics
    11. 6.11 Timing Requirements
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Over-Range Functional Characteristics
    2. 7.2 Input Clock Divider and Clock Phase Adjustment Functional Characteristics
    3. 7.3 JESD204B Interface Functional Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Amplitude and Phase Imbalance Correction of Differential Analog Input
      2. 8.3.2  DC Offset Correction
      3. 8.3.3  Over-Range Detection
      4. 8.3.4  Input Clock Divider
      5. 8.3.5  SYSREF Offset Feature and Detection Gate
      6. 8.3.6  Sampling Instant Phase Adjustment
      7. 8.3.7  Serial Differential Output Drivers
        1. 8.3.7.1 De-Emphasis Equalization
      8. 8.3.8  ADC Core Calibration
      9. 8.3.9  Data Format
      10. 8.3.10 JESD204B Supported Features
      11. 8.3.11 Transport Layer Configuration
        1. 8.3.11.1 Lane Configuration
        2. 8.3.11.2 Frame Format
        3. 8.3.11.3 ILA Information
      12. 8.3.12 Test Pattern Sequences
      13. 8.3.13 JESD204B Link Initialization
      14. 8.3.14 SPI
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down and Sleep Modes
    5. 8.5 Register Map
      1. 8.5.1 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input Considerations
        1. 9.1.1.1 Differential Analog Inputs and Full Scale Range
        2. 9.1.1.2 Analog Input Network Model
        3. 9.1.1.3 Input Bandwidth
        4. 9.1.1.4 Driving the Analog Input
        5. 9.1.1.5 Clipping and Over-Range
      2. 9.1.2 CLKIN, SYSREF, and SYNCb Input Considerations
        1. 9.1.2.1 Driving the CLKIN+ and CLKIN- Input
        2. 9.1.2.2 Clock Noise and Edge Rate
        3. 9.1.2.3 Driving the SYSREF Input
        4. 9.1.2.4 SYSREF Signaling
        5. 9.1.2.5 SYSREF Timing
        6. 9.1.2.6 Effectively Using the SYSREF Offset and Detection Gate Features
        7. 9.1.2.7 Driving the SYNCb Input
      3. 9.1.3 Output Serial Interface Considerations
        1. 9.1.3.1 Output Serial-Lane Interface
        2. 9.1.3.2 Voltage Swing and De-Emphasis Optimization
        3. 9.1.3.3 Minimizing EMI
      4. 9.1.4 JESD204B System Considerations
        1. 9.1.4.1 Frame and LMFC Clock Alignment Procedure
        2. 9.1.4.2 Link Interruption
        3. 9.1.4.3 Synchronization Requests and SYNCb Alignment in Multi-Device Systems
        4. 9.1.4.4 Clock Configuration Examples
        5. 9.1.4.5 Configuring the JESD204B Receiver
      5. 9.1.5 SPI
    2. 9.2 Typical Application
      1. 9.2.1 High-IF Sampling Receiver
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Design Procedure
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Design
    2. 10.2 Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Specification Definitions
      2. 12.1.2 JESD204B Definitions
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendations

10.1 Power Supply Design

The ADC16DX370 device is a very-high dynamic range device and therefore requires very-low noise power supplies. LDO-type regulators, capacitive decoupling, and series isolation devices like ferrite beads are all recommended.

LDO-type low noise regulators should be used to generate the 1.2-, 1.8-, and 3.0-V supplies used by the device. To improve power efficiency, a switching-type regulator may precede the LDO to efficiently drop a supply to an intermediate voltage that satisfies the drop-out requirements of the LDO. TI recommends to follow a switching-type regulator with an LDO to provide the best filtering of the switching noise. Additional ferrite beads and LC filters may be used to further suppress noise. Supplying power to multiple devices in a system from one regulator may result in noise coupling between the multiple devices; therefore, series isolation devices and additional capacitive decoupling is recommended to improve the isolation.

The power supplies must be applied to the ADC16DX370 device in this specific order:

  1. VA3.0
  2. VA1.8
  3. VA1.2
  4. VD1.2

First, the VA3.0 (+3.0 V) must be applied to provide the bias for the ESD diodes. The VA1.8 (+1.8-V) supply should be applied next, followed by the VA1.2 (+1.2-V) supply, and then followed by the VD1.2 (+1.2-V) supply. As a guideline, each supply should stabilize to within 20% of the final value within 10 ms and before enabling the next supply in the sequence. If the stabilization time is longer than 10 ms, then the system should perform the calibration procedure after the supplies have stabilized. Turning power supplies off should occur in the reverse order. An alternate power-up sequence is also supported which allows enabling the 1.2-V supplies in any order or at the same time. The alternate sequence is:

  1. VA3.0
  2. VA1.2 / VD1.2
  3. VA1.8

10.2 Decoupling

Decoupling capacitors must be used at each supply pin to prevent supply or ground noise from degrading the dynamic performance of the ADC and to provide the ADC with a well of charge to minimize voltage ripple caused by current transients. The recommended supply decoupling scheme is to have a ceramic X7R 0201 0.01-μF and a X7R 0402 0.1-μF capacitor at each supply pin. The 0201 capacitor must be placed on the same layer as the device as close to the pin as possible to minimize the AC decoupling path length from the supply pin, through the capacitor, to the nearest adjacent ground pin. The 0402 capacitor should also be close to the pins. TI does not recommend placing the capacitor on the opposite board side. Each voltage supply should also have a single 10-μF decoupling capacitor near the device but the proximity to the supply pins is less critical.

The BP2.5 pin is an external bypass pin used for stabilizing an internal 2.5-V regulator and must have a ceramic or tantalum 10-μF capacitor and a ceramic 0402 0.1-μF capacitor. The 0.1-μF capacitor should be placed as close to the BP2.5 pin as possible.