SNVSA18C Data sheet

SNVSA18C April 2014 – August 2014 ADC16DX370

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

RME|56
- MPQF397

Thermal pad, mechanical data (Package|Pins)

Orderable Information

5 Pin Configuration and Functions

WQFN PACKAGE

56 PINS

(TOP VIEW)

Pin Functions

PIN		TYPE OR DIAGRAM	DESCRIPTION
NAME	NUMBER	TYPE OR DIAGRAM	DESCRIPTION
AGND	3, 6, 9, 12, 16, 19, 22, 31, 40, 49, 52, 55	Analog ground	Analog ground Must be connected to a solid ground reference plane under the device.
BP2.5	41	Bypass pins	Capacitive bypassing pin for internally regulated 2.5-V supply This pin must be decoupled to AGND with a 0.1-μF and a 10-µF capacitor located close to the pin.
CLKIN+, CLKIN–	17, 18		Differential device clock input pins Each pin is internally terminated to a DC bias with a 50-Ω resistor for a 100-Ω total internal differential termination. AC coupling is required for coupling the clock input to these pins if the clock driver cannot meet the common-mode requirements. Sampling occurs on the rising edge of the differential signal (CLKIN+) − (CLKIN–).
CSB	54		SPI chip select pin When this signal is asserted, SCLK is used to clock the input serial data on the SDI pin or output serial data on the SDO pin. When this signal is de-asserted, the SDO pin is high impedance and the input data is ignored. Active low. A 10 kΩ pull-up resistor to the VA1.8 supply is recommended to prevent undesired activation of the SPI bus. Compatible with 1.2- to 3.0-V CMOS logic levels.
DGND	25, 46	Digital ground	Digital ground Must be connected to the same solid ground reference plane under the device to which AGND connects. Bypass capacitors connected to the VD1.2 pins must be connected to ground as close to this DGND pins as possible.
OVRA, OVRB	44, 43		Over-range detection outputs These pins output the channel A and channel B over-range signals as 1.8-V CMOS logic level outputs.
SA0+, SA0–, SA1+, SA1–	38, 39, 36, 37		Differential high speed serial data lane pins for channel A These pins must be AC coupled to the receiving device. The differential trace routing from these pins must maintain a 100-Ω characteristic impedance. In single-lane mode, SA0+ or SAO– is used to transfer data and SA1+ or SA1– is undefined and may be left floating.
SB0+, SB0–, SB1+, SB1–	32, 33, 34, 35		Differential high speed serial data lane pins for channel B. These pins must be AC coupled to the receiving device. The differential trace routing from these pins must maintain a 100-Ω characteristic impedance. In single-lane mode, SB0+ or SB0– is used to transfer data and SB1+ and SB1– is undefined and may be left floating.
SCLK	53		SPI serial clock pin Serial data is shifted into and out of the device synchronous with this clock signal. Compatible with 1.2- to 3.0-V CMOS logic levels.
SDI	47		SPI data input pin Serial data is shifted into the device on this pin while the CSB signal is asserted. Compatible with 1.2- to 3.0-V CMOS logic levels.
SDO	48		SPI data output pin Serial data is shifted out of the device on this pin during a read command while CSB is asserted. The output logic level is configurable as 1.2, 1.8, 2.5, or 3.0 V. The output level must be configured after power up and before performing a read command. See the Register Descriptions for configuration details.
SYNCb+, SYNCb–	27, 28		Differential SYNCb signal input pins DC coupling is required for coupling the SYNCb signal to these pins. Each pin is internally terminated to the DC bias with a large resistor. An internal 100-Ω differential termination is provided therefore an external termination is not required. Additional resistive components in the input structure give the SYNCb input a wide input common-mode range. The SYNCb signal is active low and therefore asserted when the voltage at SYNCb+ is less than at SYNCb–.
SYSREF+, SYSREF–	23, 24		Differential SYSREF signal input pins Each pin is internally terminated to a DC bias with a 1-kΩ resistor. An external 100-Ω differential termination must always be provided. AC coupling using capacitors is required for coupling the SYSREF signal to these pins if the clock driver cannot meet the common-mode requirements. In the case of AC coupling, the termination must be placed on the source side of the coupling capacitors.
VA1.2	8, 21, 30, 50	Supply input pin	1.2-V analog power supply pins These pins must be connected to a quiet source and decoupled to AGND with a 0.1-μF and 0.01-μF capacitor located close to each pin.
VA1.8	7, 15, 20, 29, 51, 56	Supply input pin	1.8-V analog power supply pins These pins must be connected to a quiet source and decoupled to AGND with a 0.1-μF and 0.01-μF capacitor located close to each pin.
VA3.0	2, 13, 42	Supply input pin	3.0-V analog power supply pin This pin must be connected to a quiet source and decoupled to AGND with a 0.1-μF and 0.01-μF capacitor located close to the pin.
VCMA, VCMB	1, 14		Input interface common mode voltage for channels A and B These pins must be bypassed to AGND with low equivalent series inductance (ESL) 0.1-μF capacitors. One capacitor should be placed as close to the pin as possible and additional capacitors placed at the bias load points. 10-μF capacitors should also be placed in parallel. TI recommends to use VCMA and VCMB to provide the common mode voltage for the differential analog inputs. The input common mode bias is provided internally for the ADC input; therefore, external use of VCMA and VCMB is recommended, but not strictly required. The recommended bypass capacitors are always required.
VD1.2	26, 45	Supply input pin	1.2-V digital power supply pin This pin must be connected to a quiet source and decoupled to AGND with a 0.1-μF and 0.01-μF capacitor located close to each pin.
VINA+, VINA–	4, 5		Differential analog input pins of channel A Each input pin is terminated to the internal common mode reference with a resistor for an internal differential termination.
VINB+, VINB–	11, 10		Differential analog input pins of channel B Each input pin is terminated to the internal common mode reference with a resistor for an internal differential termination.
	0	Exposed thermal pad	Exposed thermal pad The exposed pad must be connected to the AGND ground plane electrically and with good thermal dissipation properties to achieve rated performance.