The output bit mapper allows to change the output bit order for any selected interface mode.
It is a two step process to change the output bit mapping and assemble the output data bus:
|Bit||Channel A||Channel B|
|Previous sample (2-w only)||Current sample||Previous sample (2-w only)||Current sample|
In parallel DDR mode, a data bit (with unique identifier) needs to be assigned to each output pin for both the rising and the falling edge of the DCLK using the register addresses as shown in Figure 8-43. The example on the right shows the output data bus remapped to where all 14 bit of channel A is output on DCLK rising edge followed by all 14 bit of channel B on DCLK falling edge.
In the serial output mode, a data bit (with unique identifier) needs to be assigned to each location within the serial output stream. There are a total of 40 addresses available per channel. Channel A spans from address 0x39 to 0x60 and channel B from address 0x61 to 0x88. When using complex decimation, the output bit mapper is applied to both the “I” and the “Q” sample.
2-wire mode: in this mode both the current and the previous sample have to be used in the address space as shown in Figure 8-44 below. The address order is different for 14/18-bit and 16/20-bit. Note: there are unused addresses between samples for resolution less than 20-bit (grey back ground), which can be skipped if not used.
In the following example (Figure 8-45), the 16-bit 2-wire serial output is reordered to where lane DA5/DB5 carries the 8 MSB and lane DA6/DB6 carries 8 LSBs.
1-wire mode: Only the ‘current’ sample needs to programmed in the address space. If desired, it can be duplicated on DA5/DB5 as well (using addresses shown below) in order to have a redundant output. Lane DA5/DB5 needs to be powered up in that case.
½-wire mode: The output is only on lane DA6 and the sample order is programmed into the 40 addresses of chA (from 0x39 to 0x60). It covers 2 samples (one for chA, one for chB) as shown below.