ADC3643

ACTIVE

Dual, 14-bit, 1-MSPS to 65-MSPS, low-noise, ultra-low-power, analog-to-digital converter (ADC)

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Data sheet

ADC3643

ACTIVE

Data sheet

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Product details

Sample rate (Max) (MSPS)

65

Resolution (Bits)

14

Number of input channels

2

Interface type

CMOS

Analog input BW (MHz)

900

Features

High Performance, Low Power

Rating

Catalog

Input range (Vp-p)

2.25

Power consumption (Typ) (mW)

144

Architecture

SAR

SNR (dB)

79

ENOB (Bits)

12.8

SFDR (dB)

93

Operating temperature range (C)

-40 to 105

Input buffer

No

Sample rate (Max) (MSPS)

65

Resolution (Bits)

14

Number of input channels

2

Interface type

CMOS

Analog input BW (MHz)

900

Features

High Performance, Low Power

Rating

Catalog

Input range (Vp-p)

2.25

Power consumption (Typ) (mW)

144

Architecture

SAR

SNR (dB)

79

ENOB (Bits)

12.8

SFDR (dB)

93

Operating temperature range (C)

-40 to 105

Input buffer

No

WQFN (RSB)

40

25 mm² 5 x 5

Dual channel
14-bit 10/25/65 MSPS ADC
Noise floor: –155 dBFS/Hz
Ultra-low power with optimized power scaling: 29 mW/ch (10 MSPS) to 72 mW/ch (65 MSPS)
Latency: 1 clock cycle
14-Bit, no missing codes
INL: ±0.6 LSB; DNL: ±0.2 LSB
Reference: external or internal
Industrial temperature range: –40°C to +105°C
On-chip digital filter (optional)
- Decimation by 2, 4, 8, 16, 32
- 32-bit NCO
DDR and Serial CMOS interface
Small footprint: 40-VQFN (5 mm × 5 mm) package
Single 1.8-V supply
Spectral performance (f_IN = 5 MHz):
- SNR: 79.0 dBFS
- SFDR: 93-dBc HD2, HD3
- SFDR: 101-dBFS worst spur
Spectral performance (f_IN = 64 MHz):
- SNR: 74.0 dBFS
- SFDR: 84-dBc HD2, HD3
- SFDR: 90-dBFS worst spur

Dual channel
14-bit 10/25/65 MSPS ADC
Noise floor: –155 dBFS/Hz
Ultra-low power with optimized power scaling: 29 mW/ch (10 MSPS) to 72 mW/ch (65 MSPS)
Latency: 1 clock cycle
14-Bit, no missing codes
INL: ±0.6 LSB; DNL: ±0.2 LSB
Reference: external or internal
Industrial temperature range: –40°C to +105°C
On-chip digital filter (optional)
- Decimation by 2, 4, 8, 16, 32
- 32-bit NCO
DDR and Serial CMOS interface
Small footprint: 40-VQFN (5 mm × 5 mm) package
Single 1.8-V supply
Spectral performance (f_IN = 5 MHz):
- SNR: 79.0 dBFS
- SFDR: 93-dBc HD2, HD3
- SFDR: 101-dBFS worst spur
Spectral performance (f_IN = 64 MHz):
- SNR: 74.0 dBFS
- SFDR: 84-dBc HD2, HD3
- SFDR: 90-dBFS worst spur

The ADC364x family of devices are low-noise, ultra-low power, 14-bit, 10-MSPS to 65-MSPS dual-channel, high-speed analog-to-digital converters (ADCs). Designed for low power consumption, these devices deliver a noise spectral density of –155 dBFS/Hz, combined with excellent linearity and dynamic range. The ADC364x offers very good dc precision, together with IF sampling support, which make the device an excellent choice for a wide range of applications. High-speed control loops benefit from the short latency of only one clock cycle. The ADC consumes only 72 mW/ch at 65 MSPS, and power consumption scales well with lower sampling rates.

The ADC364x use a DDR or serial CMOS interface to output the data offering lowest power digital interface, together with flexibility to minimize the number of digital interconnects. These devices are a pin-to-pin compatible family with different speed grades. These devices support the extended industrial temperature range of –40 to +105⁰C.

The ADC364x family of devices are low-noise, ultra-low power, 14-bit, 10-MSPS to 65-MSPS dual-channel, high-speed analog-to-digital converters (ADCs). Designed for low power consumption, these devices deliver a noise spectral density of –155 dBFS/Hz, combined with excellent linearity and dynamic range. The ADC364x offers very good dc precision, together with IF sampling support, which make the device an excellent choice for a wide range of applications. High-speed control loops benefit from the short latency of only one clock cycle. The ADC consumes only 72 mW/ch at 65 MSPS, and power consumption scales well with lower sampling rates.

The ADC364x use a DDR or serial CMOS interface to output the data offering lowest power digital interface, together with flexibility to minimize the number of digital interconnects. These devices are a pin-to-pin compatible family with different speed grades. These devices support the extended industrial temperature range of –40 to +105⁰C.

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Technical documentation

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	Type	Title	Date
*	Data sheet	ADC364x 14-bit, 10-MSPS to 65-MSPS, Low-Noise, Low Power Dual Channel ADC datasheet	20 Sep 2017
	Technical article	How smart AFEs offer an integrated analog solution for thermoelectric cooling control	04 Jan 2022
	Application note	High-Speed ADC: How to Properly Terminate Single-ended CMOS Digital Outputs	09 Dec 2020
	Application note	High Speed SAR ADC: Data Rate, Performance, and Pin Count Optimization	08 Dec 2020
	Technical article	Keys to quick success using high-speed data converters	13 Oct 2020
	Analog design journal	How to simplify AFE filtering via high‐speed ADCs with internal digital filters	10 Jan 2020
	User guide	ADC364xEVM User's Guide	11 Nov 2019
	Technical article	How to achieve fast frequency hopping	03 Mar 2019
	Technical article	RF sampling: Learning more about latency	09 Feb 2017

Design & development

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Evaluation board

ADC3643EVM — ADC3643 dual, 14-bit, 1-MSPS to 65-MSPS, low-noise, ultra-low-power ADC evaluation module

The ADC3643 evaluation module (EVM) demonstrates the performance of the ADC3643, which is an ultra-low-power, high-linearity, analog-to-digital converter (ADC). Onboard voltage regulation and flexible analog input options allow easy evaluation for many different applications.

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Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)

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Simulation model

ADC35xx TINA Reference Design

SBAM455.ZIP (158 KB) - TINA-TI Reference Design

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PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)

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