SBASAP7A December   2024  – April 2025 ADC3664-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Bandwidth
        2. 7.3.1.2 Analog Front End Design
          1. 7.3.1.2.1 Sampling Glitch Filter
          2. 7.3.1.2.2 AC Coupling
          3. 7.3.1.2.3 DC Coupling
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Differential Vs Single-ended Clock Input
        2. 7.3.2.2 Signal Acquisition Time Adjust
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal Voltage Reference
        2. 7.3.3.2 External Voltage Reference
      4. 7.3.4 Digital Data Path & Interface
        1. 7.3.4.1 Data Path Overview
        2. 7.3.4.2 Digital Interface
        3. 7.3.4.3 DCLKIN
        4. 7.3.4.4 Output Scrambler
        5. 7.3.4.5 Output Bit Mapper
          1. 7.3.4.5.1 2-Wire Mode
          2. 7.3.4.5.2 1-Wire Mode
          3. 7.3.4.5.3 1/2-Wire Mode
        6. 7.3.4.6 Output Data Format
        7. 7.3.4.7 Test Pattern
      5. 7.3.5 Digital Down Converter
        1. 7.3.5.1 Decimation Operation
        2. 7.3.5.2 Numerically Controlled Oscillator (NCO)
        3. 7.3.5.3 Decimation Filters
        4. 7.3.5.4 SYNC
        5. 7.3.5.5 Output Data Format with Decimation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Latency Mode
      2. 7.4.2 Averaging Mode
    5. 7.5 Programming
      1. 7.5.1 Pin Control
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
      3. 7.5.3 Device Configuration Steps
      4. 7.5.4 Register Map
        1. 7.5.4.1 Detailed Register Description
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HBP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.9 Typical Characteristics

Typical values at TA = 25°C, ADC sampling rate = 125MSPS, FIN = 5MHz, AIN = –1dBFS differential input, AVDD = IOVDD = 1.8V, external 1.6V voltage reference, unless otherwise noted.

ADC3664-SP Single Tone Spectrum At FIN = 5MHz, AIN = -1, -20dBFS
SNR = 77.2dBFS, SFDR = 82.9dBc, Non HD23 = 93.2dBc
-20dBFS: SNR = 78.5dBFS, SFDR = 74.1dBc, Non HD23 = 75.6dBc
Figure 5-1 Single Tone Spectrum At FIN = 5MHz, AIN = -1, -20dBFS
ADC3664-SP Single Tone Spectrum At FIN = 40MHz
SNR = 75.8dBFS, SFDR = 81.7dBc, Non HD23 = 90.8dBc
Figure 5-3 Single Tone Spectrum At FIN = 40MHz
ADC3664-SP Single Tone Spectrum At FIN = 100MHz
SNR = 72.1dBFS, SFDR = 75dBc, Non HD23 = 78.1dBc
Figure 5-5 Single Tone Spectrum At FIN = 100MHz
ADC3664-SP Two Tone Spectrum At FIN = 90/92MHz, AIN = -7 and -20dBFS/tone
-7dBFS: IMD3 = 77.8dBc
-20dBFS: IMD3 = 85.7dBc
Figure 5-7 Two Tone Spectrum At FIN = 90/92MHz, AIN = -7 and -20dBFS/tone
ADC3664-SP ENOB Vs Input Frequency
Figure 5-9 ENOB Vs Input Frequency
ADC3664-SP AC Performance Vs Sampling Rate
FIN = 5MHz
Figure 5-11 AC Performance Vs Sampling Rate
ADC3664-SP AC Performance Vs AVDD
FIN = 5MHz
Figure 5-13 AC Performance Vs AVDD
ADC3664-SP INL Vs Code
Figure 5-15 INL Vs Code
ADC3664-SP DC Offset Histogram
No input signal
Figure 5-17 DC Offset Histogram
ADC3664-SP Current Vs Sampling Rate
FIN = 5MHz, DDC Bypass
Figure 5-19 Current Vs Sampling Rate
ADC3664-SP IIOVDD Current Vs Output Interface
FIN = 5MHz, Complex Decimation by 32
Figure 5-21 IIOVDD Current Vs Output Interface
ADC3664-SP Single Tone Spectrum At FIN = 10MHz
SNR = 77.1dBFS, SFDR = 82.8dBc, Non HD23 = 92.4dBc
Figure 5-2 Single Tone Spectrum At FIN = 10MHz
ADC3664-SP Single Tone Spectrum At FIN = 70MHz
SNR = 74.1dBFS, SFDR = 75.5dBc, Non HD23 = 81.4dBc
Figure 5-4 Single Tone Spectrum At FIN = 70MHz
ADC3664-SP Two Tone Spectrum At FIN = 10/12MHz, AIN = -7, -20dBFS/tone
-7dBFS: IMD3 = 80.1dBc
-20dBFS: IMD3 = 89.6dBc
Figure 5-6 Two Tone Spectrum At FIN = 10/12MHz, AIN = -7, -20dBFS/tone
ADC3664-SP AC Performance Vs Input Frequency
Figure 5-8 AC Performance Vs Input Frequency
ADC3664-SP AC Performance Vs Input Amplitude
FIN = 5MHz
Figure 5-10 AC Performance Vs Input Amplitude
ADC3664-SP AC Performance Vs Clock Amplitude
Figure 5-12 AC Performance Vs Clock Amplitude
ADC3664-SP Isolation Vs Input Frequency
Figure 5-14 Isolation Vs Input Frequency
ADC3664-SP DNL Vs Code
Figure 5-16 DNL Vs Code
ADC3664-SP Pulse Response
Unwrapped 1MHz Square Wave
Figure 5-18 Pulse Response
ADC3664-SP IIOVDD Current Vs Decimation
FIN = 5MHz, 2-wire
Figure 5-20 IIOVDD Current Vs Decimation