SBASAP7A December   2024  – April 2025 ADC3664-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Bandwidth
        2. 7.3.1.2 Analog Front End Design
          1. 7.3.1.2.1 Sampling Glitch Filter
          2. 7.3.1.2.2 AC Coupling
          3. 7.3.1.2.3 DC Coupling
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Differential Vs Single-ended Clock Input
        2. 7.3.2.2 Signal Acquisition Time Adjust
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal Voltage Reference
        2. 7.3.3.2 External Voltage Reference
      4. 7.3.4 Digital Data Path & Interface
        1. 7.3.4.1 Data Path Overview
        2. 7.3.4.2 Digital Interface
        3. 7.3.4.3 DCLKIN
        4. 7.3.4.4 Output Scrambler
        5. 7.3.4.5 Output Bit Mapper
          1. 7.3.4.5.1 2-Wire Mode
          2. 7.3.4.5.2 1-Wire Mode
          3. 7.3.4.5.3 1/2-Wire Mode
        6. 7.3.4.6 Output Data Format
        7. 7.3.4.7 Test Pattern
      5. 7.3.5 Digital Down Converter
        1. 7.3.5.1 Decimation Operation
        2. 7.3.5.2 Numerically Controlled Oscillator (NCO)
        3. 7.3.5.3 Decimation Filters
        4. 7.3.5.4 SYNC
        5. 7.3.5.5 Output Data Format with Decimation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Latency Mode
      2. 7.4.2 Averaging Mode
    5. 7.5 Programming
      1. 7.5.1 Pin Control
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
      3. 7.5.3 Device Configuration Steps
      4. 7.5.4 Register Map
        1. 7.5.4.1 Detailed Register Description
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HBP|64
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics - DC Specifications

Typical values are at TA = 25°C, full temperature range is TMIN = –55°C to TMAX = 105°C, ADC sampling rate = 125MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8V, 1.6V external reference, and –1dBFS differential input, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY
No missing codes 14 bits
PSRR Power supply rejection ratio FIN = 1MHz 35 dB
DNL Differential nonlinearity FIN = 5MHz ±0.9 ±0.97 LSB
INL Integral nonlinearity FIN = 5MHz ±2.6 ±9.5 LSB
VOS Input offset ±30 ±50 LSB
VOS_DRIFT Offset drift ±0.06 LSB/ºC
Error Gain error and internal reference combined error Both channels are powered up ±2 %FSR
Gain error Both channels are powered up ±1.8 %FSR
Gain drift External 1.6V reference ±57 ppm/ºC
Internal reference 106 ppm/ºC
Transition noise 0.7 LSB
ADC ANALOG INPUT (AINP/M, BINP/M)
FS Input full scale Differential 3.2 Vpp
VCM Input common-mode voltage 0.95 V
RIN Input resistance Differential at DC 8 kΩ
CIN Input capacitance Differential at DC 5.4 pF
VOCM Output common-mode voltage 0.95 V
BW Full power analog input bandwidth (-3dB) 200 MHz
INTERNAL VOLTAGE REFERENCE
VREF Internal reference voltage 1.6 V
VREF output impedance 8 Ω
EXTERNAL VOLTAGE REFERENCE
VREF External voltage reference 1.6 V
Input current 1 mA
Input impedance 5.3 kΩ
CLOCK INPUT (CLKP/M)
Input clock frequency External reference 1 125 MHz
Internal reference 100 125 MHz
VID Differential input voltage 0.5 1 Vpp
VCM Input common-mode voltage 0.9 V
RIN Single ended input resistance to common mode 5 kΩ
CIN Single ended input capacitance 1.5 pF
Clock duty cycle 45 50 60 %
DIGITAL INPUTS (RESET, PDN, SCLK, SEN, SDIO)
VIH High level input voltage 1.5 V
VIL Low level input voltage 0.3
IIH High level input current 90 150 uA
IIL Low level input current -150 -90 uA
CI Input capacitance 1.5 pF
DIGITAL OUTPUT (SDOUT)
VOH High level output voltage ILOAD = -400 uA IOVDD – 0.1 IOVDD V
VOL Low level output voltage ILOAD = 400 uA 0.1
LVDS lane rate 1 Gbps
VID DCLKIN differential input voltage 200 350 mVpp
VCM DCLKIN input common-mode voltage 1.1 1.2 1.3 V
SLVDS INTERFACE
VOD Differential output voltage 0.585 700 0.785 mVpp
VCM Output common-mode voltage 0.85 1.0 1.15 V