SBAS872 December   2020 ADC3683


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics - ADC3683
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. Analog Input Bandwidth
        2. Analog Front End Design
          1. Sampling Glitch Filter Design
          2. Analog Input Termination and DC Bias
            1. AC-Coupling
            2. DC-Coupling
        3. Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. Single Ended vs Differential Clock Input
        2. Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. Internal voltage reference
        2. External voltage reference (VREF)
        3. External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. DDC MUX
        2. Digital Filter Operation
        3. FS/4 Mixing with Real Output
        4. Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. Decimation Filter
        6. SYNC
        7. Output Formatting with Decimation
      5. 8.3.5 Digital Interface
        1. Output Formatter
        2. Output Interface/Mode Configuration
          1. Configuration Example
        3. Output Data Format
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Power Down Options
      3. 8.4.3 Digital Channel Averaging
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. Register Write
        2. Register Read
    6. 8.6 Register Map
      1. 8.6.1 Detailed Register Description
  9. Application Information Disclaimer
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. Input Signal Path
        2. Sampling Clock
        3. Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power Supply Recommendations

The ADC368x requires two different power-supplies. The AVDD rail provides power for the internal analog circuits and the ADC itself while the IOVDD rail powers the digital interface and the internal digital circuits like decimation filter or output interface mapper. Power sequencing is not required.

The AVDD power supply must be low noise in order to achieve data sheet performance. In applications operating near DC, the 1/f noise contribution of the power supply needs to be considered as well. The ADC is designed for very good PSRR which aides with the power supply filter design.

GUID-20200911-CA0I-HTP1-R4LL-S3NXKNT1V6L4-low.gif Figure 10-1 Power supply rejection ratio (PSRR) vs frequency

There are two recommended power-supply architectures:

  1. 1. Step down using high-efficiency switching converters, followed by a second stage of regulation using a low noise LDO to provide switching noise reduction and improved voltage accuracy.
  2. 2. Directly step down the final ADC supply voltage using high-efficiency switching converters. This approach provides the best efficiency, but care must be taken to ensure switching noise is minimized to prevent degraded ADC performance.

TI WEBENCH® Power Designer can be used to select and design the individual power-supply elements needed: see the WEBENCH® Power Designer

Recommended switching regulators for the first stage include the TPS62821, and similar devices.

Recommended low dropout (LDO) linear regulators include the TPS7A4701, TPS7A90, LP5901, and similar devices.

For the switch regulator only approach, the ripple filter must be designed with a notch frequency that aligns with the switching ripple frequency of the DC/DC converter. Note the switching frequency reported from WEBENCH® and design the EMI filter and capacitor combination to have the notch frequency centered as needed. Figure 10-2 and Figure 10-3 illustrate the two approaches.

AVDD and IOVDD supply voltages should not be shared in order to prevent digital switching noise from coupling into the analog signal chain.

GUID-FB798F7D-5688-45ED-A142-5F756B762468-low.gif Figure 10-2 Example: LDO Linear Regulator Approach
GUID-36F8A281-B686-408E-A84F-EB03B6D2E132-low.gif Figure 10-3 Example Switcher-Only Approach