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High-speed ADCs (>10MSPS)

ADC3683

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Dual-channel, 18-bit, 65-MSPS, low-noise, ultra-low-power analog-to-digital converter (ADC)

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Data sheet

ADC3683

ACTIVE
Data sheet Order now

Product details

Sample rate (Max) (MSPS) 65 Resolution (Bits) 18 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 900 Features High Dynamic Range, High Performance, Low Power Rating Catalog Input range (Vp-p) 3.2 Power consumption (Typ) (mW) 186 Architecture SAR SNR (dB) 83.8 ENOB (Bits) 13.7 SFDR (dB) 89 Operating temperature range (C) -40 to 105 Input buffer No
Sample rate (Max) (MSPS) 65 Resolution (Bits) 18 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 900 Features High Dynamic Range, High Performance, Low Power Rating Catalog Input range (Vp-p) 3.2 Power consumption (Typ) (mW) 186 Architecture SAR SNR (dB) 83.8 ENOB (Bits) 13.7 SFDR (dB) 89 Operating temperature range (C) -40 to 105 Input buffer No
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WQFN (RSB) 40 25 mm² 5 x 5
open-in-new Find other High-speed ADCs (>10MSPS)
  • Dual channel ADC
  • 18-bit 10, 25, 65 MSPS ADC
  • Noise floor: -160 dBFS/Hz
  • Low power and optimized power scaling: 50 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS)
  • Latency: 1-2 clock cycles
  • 18-bit, no missing codes
  • INL/DNL: ±7/ ±0.7 LSB (typical)
  • Reference: external or internal
  • Input bandwidth: 900 MHz (3-dB)
  • Industrial temperature range: -40 to +105°C
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • Serial LVDS digital interface (2-, 1- and 1/2-wire)
  • Small footprint: 40-QFN (5x5 mm) package
  • Spectral performance (fIN = 5 MHz):
    • SNR: 83.8 dBFS
    • SFDR: 89 dBc HD2, HD3
    • SFDR: 101 dBFS Worst spur
  • Spectral performance (fIN = 20 MHz):
    • SNR: 82.6 dBFS
    • SFDR: 85 dBc HD2, HD3
    • SFDR: 97 dBFS Worst spur
  • Dual channel ADC
  • 18-bit 10, 25, 65 MSPS ADC
  • Noise floor: -160 dBFS/Hz
  • Low power and optimized power scaling: 50 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS)
  • Latency: 1-2 clock cycles
  • 18-bit, no missing codes
  • INL/DNL: ±7/ ±0.7 LSB (typical)
  • Reference: external or internal
  • Input bandwidth: 900 MHz (3-dB)
  • Industrial temperature range: -40 to +105°C
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • Serial LVDS digital interface (2-, 1- and 1/2-wire)
  • Small footprint: 40-QFN (5x5 mm) package
  • Spectral performance (fIN = 5 MHz):
    • SNR: 83.8 dBFS
    • SFDR: 89 dBc HD2, HD3
    • SFDR: 101 dBFS Worst spur
  • Spectral performance (fIN = 20 MHz):
    • SNR: 82.6 dBFS
    • SFDR: 85 dBc HD2, HD3
    • SFDR: 97 dBFS Worst spur
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The ADC3681, 82, 83 (ADC368x) is a low noise, ultra-low power 18-bit 65 MSPS high-speed dual channel ADC family. Designed for lowest noise performance, it delivers a noise spectral density of -160 dBFS/Hz combined with excellent linearity and dynamic range. The ADC368x offers excellent DC precision together with IF sampling support which makes it ideally suited for a wide range of applications. High-speed control loops benefit from the short latency as low as only 1 clock cycle. The ADC consumes only 94 mW/ch at 65 Msps and its power consumption scales very well with lower sampling rates.

The ADC368x uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device supports two-lane, one-lane and half-lane options. The ADC36xx is a pin to pin compatible family of ADCs with 16 and 18-bit resolution and different speed grades. It comes in a 40-pin QFN package (5 x 5mm) and supports the extended industrial temperature range from -40 to +105⁰C.

The ADC3681, 82, 83 (ADC368x) is a low noise, ultra-low power 18-bit 65 MSPS high-speed dual channel ADC family. Designed for lowest noise performance, it delivers a noise spectral density of -160 dBFS/Hz combined with excellent linearity and dynamic range. The ADC368x offers excellent DC precision together with IF sampling support which makes it ideally suited for a wide range of applications. High-speed control loops benefit from the short latency as low as only 1 clock cycle. The ADC consumes only 94 mW/ch at 65 Msps and its power consumption scales very well with lower sampling rates.

The ADC368x uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device supports two-lane, one-lane and half-lane options. The ADC36xx is a pin to pin compatible family of ADCs with 16 and 18-bit resolution and different speed grades. It comes in a 40-pin QFN package (5 x 5mm) and supports the extended industrial temperature range from -40 to +105⁰C.

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Technical documentation

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Type Title Date
* Data sheet ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC datasheet (Rev. A) 14 Dec 2021
Technical article How smart AFEs offer an integrated analog solution for thermoelectric cooling control 04 Jan 2022
Certificate ADC3683EVM EU RoHS Declaration of Conformity (DoC) 23 Dec 2020
Application note High Speed SAR ADC: Data Rate, Performance, and Pin Count Optimization 08 Dec 2020
User guide ADC368xEVM User's Guide 30 Oct 2020
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
Application note High Speed ADCs and Amplifiers for Flow Cytometry Applications 12 Oct 2020
Analog design journal How to simplify AFE filtering via high‐speed ADCs with internal digital filters 10 Jan 2020
Technical article How to achieve fast frequency hopping 03 Mar 2019
Technical article RF sampling: Learning more about latency 09 Feb 2017

Design & development

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Evaluation board

ADC3683EVM — ADC3683 dual-channel, 18-bit, 65-MSPS, low-noise, ultra-low-power ADC evaluation module

The ADC3683 evaluation module (EVM) is a platform that demonstrates the performance of the ultra-low-power, high-linearity ADC3683. Onboard voltage regulation and flexible analog input options allow easy evaluation for many different applications.

For a complete evaluation system, use the TSW1400EVM (...)

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Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
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Simulation model

ADC36XX IBIS Model

SBAM400.ZIP (52 KB) - IBIS Model
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Simulation model

ADC35xx TINA Reference Design

SBAM455.ZIP (158 KB) - TINA-TI Reference Design
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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