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High-speed ADCs (≥10 MSPS)
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ADC3682

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Dual-channel, 18-bit, 25-MSPS, low-noise, ultra-low-power, low-latency ADC

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Data sheet

ADC3682

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 25 Resolution (Bps) 18 Number of input channels 2 Interface type DDR LVDS Analog input BW (MHz) 900 Features High Dynamic Range, High Performance, Low Power, Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 3.2 Power consumption (typ) (mW) 110 Architecture SAR SNR (dB) 86 ENOB (Bps) 13.7 SFDR (dB) 90 Operating temperature range (°C) -40 to 105 Input buffer No
Sample rate (max) (Msps) 25 Resolution (Bps) 18 Number of input channels 2 Interface type DDR LVDS Analog input BW (MHz) 900 Features High Dynamic Range, High Performance, Low Power, Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 3.2 Power consumption (typ) (mW) 110 Architecture SAR SNR (dB) 86 ENOB (Bps) 13.7 SFDR (dB) 90 Operating temperature range (°C) -40 to 105 Input buffer No
WQFN (RSB) 40 25 mm² 5 x 5
  • Dual channel ADC
  • 18-bit 10, 25, 65 MSPS ADC
  • Noise floor: -160 dBFS/Hz
  • Low power and optimized power scaling: 53 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS)
  • Latency: 1-2 clock cycles
  • 18-bit, no missing codes
  • INL/DNL: ±7/ ±0.7 LSB (typical)
  • Reference: external or internal
  • Input bandwidth: 900 MHz (3-dB)
  • Industrial temperature range: -40 to +105°C
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • Serial LVDS digital interface (2-, 1- and 1/2-wire)
  • Small footprint: 40-QFN (5x5 mm) package
  • Spectral performance (fIN = 5 MHz):
    • SNR: 83.8 dBFS
    • SFDR: 89 dBc HD2, HD3
    • SFDR: 101 dBFS Worst spur
  • Spectral performance (fIN = 20 MHz):
    • SNR: 82.6 dBFS
    • SFDR: 85 dBc HD2, HD3
    • SFDR: 97 dBFS Worst spur
  • Dual channel ADC
  • 18-bit 10, 25, 65 MSPS ADC
  • Noise floor: -160 dBFS/Hz
  • Low power and optimized power scaling: 53 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS)
  • Latency: 1-2 clock cycles
  • 18-bit, no missing codes
  • INL/DNL: ±7/ ±0.7 LSB (typical)
  • Reference: external or internal
  • Input bandwidth: 900 MHz (3-dB)
  • Industrial temperature range: -40 to +105°C
  • On-chip digital filter (optional)
    • Decimation by 2, 4, 8, 16, 32
    • 32-bit NCO
  • Serial LVDS digital interface (2-, 1- and 1/2-wire)
  • Small footprint: 40-QFN (5x5 mm) package
  • Spectral performance (fIN = 5 MHz):
    • SNR: 83.8 dBFS
    • SFDR: 89 dBc HD2, HD3
    • SFDR: 101 dBFS Worst spur
  • Spectral performance (fIN = 20 MHz):
    • SNR: 82.6 dBFS
    • SFDR: 85 dBc HD2, HD3
    • SFDR: 97 dBFS Worst spur

The ADC3681, 82, 83 (ADC368x) is a low noise, ultra-low power 18-bit 65 MSPS high-speed dual channel ADC family. Designed for lowest noise performance, it delivers a noise spectral density of -160 dBFS/Hz combined with excellent linearity and dynamic range. The ADC368x offers excellent DC precision together with IF sampling support which makes it suited for a wide range of applications. High-speed control loops benefit from the short latency as low as only 1 clock cycle. The ADC consumes only 94 mW/ch at 65 Msps and its power consumption scales well with lower sampling rates.

The ADC368x uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device supports two-lane, one-lane and half-lane options. The ADC36xx is a pin to pin compatible family of ADCs with 16 and 18-bit resolution and different speed grades. It comes in a 40-pin QFN package (5 x 5mm) and supports the extended industrial temperature range from -40 to +105⁰C.

The ADC3681, 82, 83 (ADC368x) is a low noise, ultra-low power 18-bit 65 MSPS high-speed dual channel ADC family. Designed for lowest noise performance, it delivers a noise spectral density of -160 dBFS/Hz combined with excellent linearity and dynamic range. The ADC368x offers excellent DC precision together with IF sampling support which makes it suited for a wide range of applications. High-speed control loops benefit from the short latency as low as only 1 clock cycle. The ADC consumes only 94 mW/ch at 65 Msps and its power consumption scales well with lower sampling rates.

The ADC368x uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital interconnects. The device supports two-lane, one-lane and half-lane options. The ADC36xx is a pin to pin compatible family of ADCs with 16 and 18-bit resolution and different speed grades. It comes in a 40-pin QFN package (5 x 5mm) and supports the extended industrial temperature range from -40 to +105⁰C.
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Our ADC3660 family won the 2021 World Electronics Achievement Awards (WEAA) Product of the Year in the Amplifier/Data Conversion category.

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* Data sheet ADC368x 18-bit 0.5 to 65-MSPS Low Noise Ultra-low Power Dual Channel ADC datasheet (Rev. B) PDF | HTML 03 Oct 2022
Application note High Speed SAR ADC: Data Rate, Performance, and Pin Count Optimization PDF | HTML 08 Dec 2020
Analog Design Journal How to simplify AFE filtering via high‐speed ADCs with internal digital filters 10 Jan 2020

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DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
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ADC35xx TINA-TI Reference Design

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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