SBAS872 December 2020 ADC3683
Applications operating with low input frequencies (such as DC to 20 MHz) typically are less sensitive to performance degradation due to clock jitter. The internal ADC aperture jitter improves with faster rise and fall times (i.e. square wave vs sine wave). Table 9-4 provides an overview of the estimated SNR performance of the ADC368x based on different amounts of jitter of the external clock source. The SNR is estimated based on ADC368x thermal noise of 84.2dBFS and input signal at -1dBFS.
|INPUT FREQUENCY||TJ,EXT = 100 fs||TJ,EXT = 250 fs||TJ,EXT = 500 fs||TJ,EXT = 1 ps|
Termination of the clock input should be considered for long clock traces.