The devices offer digital filter options for both filtering and decimation of the digital data stream coming from the delta-sigma modulator. The implementation of the digital filter is determined by the data rate and filter mode setting. Figure 53 shows the digital filter implementation. Choose between a third-order sinc filter (sinc3) and a low-latency filter (low-latency filter with multiple components) using the FILTER bit in the data rate register (04h).
NOTE:LL filter = low-latency filter.
Regardless of the FILTER type setting, the oversampling ratio is the same for each given data rate, meaning that the device requires a set number of modulator clocks to output a single ADC conversion data. The output data rate is selected using the DR[3:0] bits in the data rate register and is shown in Table 11.
|NOMINAL DATA RATE|
|DATA RATE REGISTER |