Power-down mode is entered by sending the POWERDOWN command. In this mode, all analog and digital circuitry is powered down for lowest power consumption regardless of the register settings. Only the internal voltage reference can be configured to stay on during power-down mode in case a faster start-up time is required. All register values retain the current settings during power-down mode. The configuration registers can be read and written in power-down mode. A WAKEUP command must be issued in order to exit power-down mode and to enter standby mode.
When the POWERDOWN command is issued, the device enters power-down mode 2 · tCLK after the seventh SCLK falling edge of the command. For lowest power consumption (on DVDD and IOVDD), stop the external clock when in power-down mode. The device does not gate the external clock when in power-down mode. Selecting the internal oscillator before sending the POWERDOWN command is recommended.
To release the device from POWERDOWN, issue the WAKEUP command to enter standby mode. The device then waits for the rising edge of the START/SYNC pin or a START command to go into conversion mode.
When in power-down mode, the device responds to the RREG, RDATA, and WAKEUP commands. The WREG and RESET commands can also be sent, but are ignored until a WAKEUP command is sent and the internal oscillator resumes operation.