SBAS660C August 2016 – June 2017 ADS124S06 , ADS124S08
Refer to the PDF data sheet for device specific package drawings
When connecting multiple devices to a single SPI bus, SCLK, DIN, and DOUT/DRDY can be safely shared by using a dedicated chip-select (CS) line for each SPI-enabled device. When CS transitions high for the respective device, DOUT/DRDY enters a tri-state mode. Therefore, DOUT/DRDY cannot be used to indicate when new data are available if CS is high. Only the dedicated DRDY pin indicates that new data are available because the DRDY pin is actively driven even when CS is high.
In some cases, the DRDY pin cannot be interfaced to the microcontroller. This scenario can occur if there are insufficient GPIO channels available on the microcontroller or if the serial interface must be galvanically isolated and thus the amount of channels must be limited. In order to evaluate when a new conversion of one of the devices is ready, the microcontroller can periodically drop CS to the respective device and poll the state of the DOUT/DRDY pin.
When CS goes low, the DOUT/DRDY pin immediately drives either high or low. If the DOUT/DRDY line drives low, new data are available. If the DOUT/DRDY line drives high, no new data are available. This procedure requires that DOUT/DRDY is forced high after reading each conversion result and before taking CS high. To make sure DOUT/DRDY is taken high, send a RREG command to read a register where the least significant bit is 1.
Retrieving data using direct read mode requires knowledge of the DRDY falling edge timing to avoid data corruption. Use the RDATA command so that valid data can be retrieved from the device at any time without concern of data corruption by a new data ready.