The serial interface clock is a noise-filtered, Schmidt-triggered input used to clock data into and out of the ADC. Input data to the ADC are latched on the falling SCLK edge and output data from the ADC are updated on the rising SCLK edge. Return SCLK low after the data sequence is complete. Even though the SCLK input has hysteresis, keep SCLK as clean as possible to prevent unintentional SCLK transitions. Avoid ringing and voltage overshoot on the SCLK input. Place a series termination resistor at the SCLK drive pin to help reduce ringing.