The ADS124S06 and ADS124S08 feature a low-drift, low-noise, high input impedance programmable gain amplifier (PGA). Figure 50 shows a simplified diagram of the PGA. The PGA consists of two chopper-stabilized amplifiers (A1 and A2) and a resistor feedback network that sets the gain of the PGA. The PGA input is equipped with an electromagnetic interference (EMI) filter and an antialiasing filter on the output.
The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128 using the GAIN[2:0] bits in the gain setting register (03h). Gain is changed inside the device using a variable resistor, RG. The differential full-scale input voltage range (FSR) of the PGA is defined by the gain setting and the reference voltage used, as shown in Equation 4:
Table 9 shows the corresponding full-scale ranges when using the internal 2.5-V reference.
The PGA must be enabled with the PGA_EN[1:0] bits of the gain setting register (03h). Setting these bits to 00 powers down and bypasses the PGA. A setting of 01 enables the PGA. The 10 and 11 settings are reserved and must not be written to the device.
With the PGA enabled, gains 64 and 128 are established in the digital domain. When the device is set to 64 or 128, the PGA is set to a gain of 32, and additional gain is established with digital scaling. The input-referred noise does still improve compared to the gain = 32 setting because the PGA is biased with a higher supply current to reduce noise.