SLAS669E September   2010  – may 2020 ADS5400-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Characteristics
    8. 6.8 Interleaving Adjustments
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Configuration
      2. 7.3.2  Voltage Reference
      3. 7.3.3  Analog Input Over-Range Recovery Error
      4. 7.3.4  Clock Inputs
      5. 7.3.5  Over Range
      6. 7.3.6  Data Scramble
      7. 7.3.7  Test Patterns
      8. 7.3.8  Die Identification and Revision
      9. 7.3.9  Die Temperature Sensor
      10. 7.3.10 Interleaving
        1. 7.3.10.1 Gain Adjustment
        2. 7.3.10.2 Offset Adjustment
        3. 7.3.10.3 Input Clock Coarse Phase Adjustment
        4. 7.3.10.4 Input Clock Fine Phase Adjustment
    4. 7.4 Device Functional Modes
      1. 7.4.1 Output Bus and Clock Options
      2. 7.4.2 Reset and Synchronization
      3. 7.4.3 LVDS
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. Table 2. Instruction Byte of the Serial Interface
    6. 7.6 Serial Register Map
      1. 7.6.1 Description of Serial Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Clocking Source for ADS5400-SP
        2. 8.2.2.2 Amplifier Selection
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Definition of Specifications
    2. 11.2 Documentation Support
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Timing Characteristics(1)

Typical values at TA = 25°C, Min and Max values over full temperature range TC,MIN = –55°C to TC,MAX = 125°C,
sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise noted)
PARAMETER TEST CONDITIONS/NOTES MIN TYP MAX UNIT
ta Aperture delay 250 ps
Aperture jitter, rms Uncertainty of sample point due to internal jitter sources 125 fs
Latency Bus A, using Single Bus Mode 7 Cycles
Bus A, using Dual Bus Mode Aligned 7.5
Bus B, using Dual Bus Mode Aligned 8.5
Bus A and B, using Dual Bus Mode Staggered 7.5
LVDS Output Timing (DATA, CLKOUT, OVR/SYNCOUT)(2)
tCLK Clock period 1 10 ns
tCLKH Clock pulse duration, high Assuming worst case 45/55 duty cycle 0.45 ns
tCLKL Clock pulse duration, low Assuming worst case 55/45 duty cycle 0.45 ns
tPD-CLKDIV2 Clock propagation delay CLKIN rising to CLKOUT rising in divide by 2 mode 1200 ps
tPD-CLKDIV4 Clock propagation delay CLKIN rising to CLKOUT rising in divide by 4 mode 1200 ps
tPD-ADATA Bus A data propagation delay CLKIN falling to Data Output transition 1400 ps
tPD-BDATA Bus B data propagation delay 1400 ps
tSU-SBM (3) Setup time, single bus mode Data valid to CLKOUT edge, 50% CLKIN duty cycle 290 (tCLK/2) - 185 ps
tH-SBM Hold time, single bus mode CLKOUT edge to Data invalid, 50% CLKIN duty cycle 410 (tCLK/2) - 65 ps
tSU-DBM Setup time, dual bus mode Data valid to CLKOUT edge, 50% CLKIN duty cycle 550 tCLK - 425 ps
tH-DBM Hold time, dual bus mode CLKOUT edge to Data invalid, 50% CLKIN duty cycle 1150 tCLK + 175 ps
tr LVDS output rise time Measured 20% to 80% 400 ps
tf LVDS output fall time 400 ps
LVDS Input Timing (RESETIN)
tRSU RESET setup time RESETP going HIGH to CLKINP going LOW 325 ps
tRH RESET hold time CLKINP going LOW to RESETP going LOW 325 ps
RESET input capacitance Differential 1 pF
RESET input current ±1 µA
SeriaL Interface Timing
tS-SDENB Setup time, serial enable SDENB falling to SCLK rising 20 ns
tH-SDENB Hold time, serial enable SCLK falling to SENDB rising 25 ns
tS-SDIO Setup time, SDIO SDIO valid to SCLK rising 10 ns
tH-SDIO Hold time, SDIO SCLK rising to SDIO transition 10 ns
fSCLK Frequency 10 MHz
tSCLK SCLK period 100 ns
tSCLKH Minimum SCLK high time 40 ns
tSCLKL Minimum SCLK low time 40 ns
tr Rise time 10pF 10 ns
tf Fall time 10pF 10 ns
tDDATA Data output delay Data output (SDO/SDIO) delay after SCLK falling, 10pF load 75 ns
(1) Timing parameters are specified by design or characterization, but not production tested.
(2) LVDS output timing measured with a differential 100Ω load placed ~4 inches from the ADS5400. Measured differential load capacitance is 3.5 pF. Measurement probes and other parasitics add ~1pF. Total approximate capacitive load is 4.5 pF differential. All timing parameters are relative to the device pins, with the loading as stated.
(3) In single bus mode at 1 GSPS (1ns clock), the minimum output setup/hold times over process and temperature provide a minimum 700 ps of data valid window, with 300 ps of uncertainity.